On Nov 10, 2007, at 2:35 PM, Sujay Phadke wrote:
Some more questions:
----------------------
question about remote_gdb listener in beta 4:
How do I use this? I thought i'd work similar to opening up a term
when we
simulate in FS mode: compile m5term, do >m5term <port number>. Here
I did: > >m5term 7000.
On the main screen, it shows connecting console, but the term
program just
hangs. There's no output there. If I press <enter>, it just shows some
garbage and hangs.
This is to attached a remote copy of gdb. You need to compile a gdb
for alpha and then you can attach it to the simulated process like you
would with the running process. See the website on debugging with gdb
for more information.
another question on the side: What does the line at the top: "import
Simulation", in the config script do? (when running in SE mode) Even
if I
dont have that line in my config script, my simulation is still
running by
doing m5.simulate(...) instead of doing Simulation.run(...). So does
including that line do anything more than just this?
You should read about the import statement in python:
http://docs.python.org/ref/import.htm
Ali
same with:
from Caches import *
My sims are working without this, so what does this line do?
Thanks,
Sujay
----- Original Message -----
From: "Steve Reinhardt" <[EMAIL PROTECTED]>
To: "M5 users mailing list" <m5-users@m5sim.org>
Sent: Friday, November 09, 2007 3:32 PM
Subject: Re: [m5-users] sims with m5 beta4 - cache stats
That is odd... the coherence protocol's a little different, but not
that different. Is this using atomic mode?
Steve
On 11/9/07, Sujay Phadke <[EMAIL PROTECTED]> wrote:
Hello,
I am running splash2 benchmarks, with the same
configuration in m5
beta 3 and 4. Here is a snapshot of the m5stats.txt for overall
l2 stats.
With Beta 4:
-------------------
system.l2.overall_accesses 8683
# number of overall (read+write) accesses
system.l2.overall_avg_miss_latency 0
# average overall miss latency
system.l2.overall_avg_mshr_miss_latency <err: div-0>
# average overall mshr miss latency
system.l2.overall_avg_mshr_uncacheable_latency <err: div-0>
# average overall mshr uncacheable latency
system.l2.overall_hits 2560
# number of overall hits
system.l2.overall_miss_latency 0
# number of overall miss cycles
system.l2.overall_miss_rate 0.705171
# miss rate for overall accesses
system.l2.overall_misses 6123
# number of overall misses
system.l2.overall_mshr_hits 0
# number of overall MSHR hits
system.l2.overall_mshr_miss_latency 0
# number of overall MSHR miss cycles
system.l2.overall_mshr_miss_rate 0
# mshr miss rate for overall accesses
system.l2.overall_mshr_misses 0
# number of overall MSHR misses
system.l2.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.l2.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
With beta 3:
------------------
system.l2.overall_accesses 1076225
# number of overall (read+write) accesses
system.l2.overall_avg_miss_latency 0
# average overall miss latency
system.l2.overall_avg_mshr_miss_latency <err: div-0>
# average overall mshr miss latency
system.l2.overall_avg_mshr_uncacheable_latency <err: div-0>
# average overall mshr uncacheable latency
system.l2.overall_hits 477093
# number of overall hits
system.l2.overall_miss_latency 0
# number of overall miss cycles
system.l2.overall_miss_rate 0.556698
# miss rate for overall accesses
system.l2.overall_misses 599132
# number of overall misses
system.l2.overall_mshr_hits 0
# number of overall MSHR hits
system.l2.overall_mshr_miss_latency 0
# number of overall MSHR miss cycles
system.l2.overall_mshr_miss_rate 0
# mshr miss rate for overall accesses
system.l2.overall_mshr_misses 0
# number of overall MSHR misses
system.l2.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.l2.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
With beta 4, it seems that the number of accesses are lesser, cache
hits/misses are different. All other parameters have been kept
the same
(num_cpus, L1, L2 sizes, DRAM size, etc).
Why this difference?
- Sujay
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