Yes,, you are right, my stats shows that no instruction is executed in
the second cpu. I was using FFM, is there any benchmark in splash2 that
would utilize both processors?
-panos
Quoting Steve Reinhardt <[EMAIL PROTECTED]>:
Oops, meant to send this to the list and not just to Ali.
---------- Forwarded message ----------
From: Steve Reinhardt <[EMAIL PROTECTED]>
Date: Dec 2, 2007 12:50 PM
Subject: Re: [m5-users] panic on partially satisfying the functional request
To: Ali Saidi <[EMAIL PROTECTED]>
No, they're not. The functional accesses Panos is seeing are probably
from syscall emulation.
If there aren't any traces from the second CPU's cache, that probably
means the application is never getting to the point of creating a
thread on the second CPU.
Steve
On Dec 2, 2007 11:36 AM, Ali Saidi <[EMAIL PROTECTED]> wrote:
Actually, now that I think about this I'm not sure that it is? Are
express snoops functional accesses?
Ali
On Dec 2, 2007, at 2:33 PM, Ali Saidi wrote:
> They're "express snoops," take a look at:
http://www.m5sim.org/wiki/index.php/Coherence_Protocol
>
>
> Ali
>
> On Dec 2, 2007, at 11:55 AM, [EMAIL PROTECTED] wrote:
>
>> Hi I am reposting my question. I am running splash2 with 2 CPUs.
>> Although I use the trace cache flag option, on the output I see no
>> traces of my second's CPU cache.
>>
>> Moreover, since I have configured my system for atomic requests,
>> who is calling the functional requests on the bus?
>>
>> Thanks
>>
>> Panos
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>> m5-users@m5sim.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>>
>
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