Hi all,
I'm modeling the interconnection, when modeling the interconnection and
simulate all the routers, I am following the bus that broadcast a packet to all
the snoop ports if dest is broadcast.
However, I came to this during debugging in timing mode with my interconnection
prototype:
m5.debug: build/ALPHA_SE/mem/cache/miss/mshr.hh:211: MSHR::Target*
MSHR::getTarget(): Assertion `hasTargets()' failed.
triggered in Cache::handleResponse at the statement:
cache_impl.hh:707: MSHR::Target *initial_tgt = mshr->getTarget();
doing a trace reveals that the broadcast request got two requests (ReadExResp)
from two nodes. (an L1 cache's memSidePort receives response first from a peer
L1's memSidePort, and then from the L2's memSidePort).
Is there any clue on top of your head about how this happens? My guess is the
peer's L1 snoops the packet and found a match, so both the peer L1 and L2 both
responsed the request, the second request got missed in the mshr because the
target has already been fulfilled. What do you think?
Thanks!
Jiayuan
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