On Dec 10, 2007 7:51 AM, Jiayuan <[EMAIL PROTECTED]> wrote: > > - You shouldn't be receiving responses from two different caches to a > > ReadExRequest no matter what is going on with MemInhibit. Only the > > owner cache should be responding, and there shouldn't be more than one > > owner at a given point in time. > > Why is that? The ReadExRequest can be sent from the L1 to the L1-L2 bus > after a write miss. At > The mean time, this requested cache block might be shared in other L1 > caches, as well as the L2. Because other L1s are snooping the bus, each > cache(L1/L2) containing a copy should send a ReadExResponse back while > invalidating its own copy theoretically, (although M5 uses the global > pointer to the packet to ensure there is only one response).
All the caches that snoop the packet should invalidate their copies, but only the owner should send a response. If there's no owner, then main memory will send the response. The fact that there's a single shared packet object is used only to emulate two wired-OR lines (MemInhibit and Shared). The former is used only to suppress main memory from responding, and the latter is used only for setting the E state. Those flags are not intended to provide any prioritization or arbitration among the caches on the bus (since a real wired-OR line isn't capable of that). There's no need for explicit invalidation acknowledgments since the bus provides orderin Your mesh may need that (since you don't have a central ordering point), but then that's a different coherence protocol. Note that if you want to have multiple responses for a given packet, each responder will have to allocate a new Packet... I just wrote up a little blurb on memroy allocation for Packets here: http://www.m5sim.org/wiki/index.php/Memory_System#Packet_allocation_protocol Steve _______________________________________________ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
