Switching topics slightly, prefetch extending the effective cache line
size was causing us some consternation, since we were never able to find
where it was documented. Do you have a reference to it? When did it
start happening?
It seems like it invalidates all software that was carefully written to
honor 64 byte cache lines.
IIRC Pentium 4 had 128 byte "sectors", but it was never fully explained
what these were, and the word died with the P4.
On 05/29/2017 05:26 PM, 'Nitsan Wakart' via mechanical-sympathy wrote:
In particular for Aeron LogBuffer false sharing on length writes can
only happen (on systems with cache line length 64b) for 0 length
messages as the data header size is 32b:
https://github.com/real-logic/Aeron/blob/e0bb87c4538125c577a653f20f5865a6d6d8dc95/aeron-client/src/main/java/io/aeron/protocol/DataHeaderFlyweight.java#L34-L34
and messages are aligned to 32b:
https://github.com/real-logic/Aeron/blob/ae85cb4d00e5f8c7eed3dd18d9ba737a4885393a/aeron-client/src/main/java/io/aeron/logbuffer/FrameDescriptor.java#L58-L58
This is ignoring prefetch induced false sharing which increases the
boundaries of this issue to 128b, but which is also less severe.
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