It's approximately where you'd expect, in the Intel 64 and IA32 Architecture Optimization Reference Manual, under "Data Prefetching" on page 2-29, and referred to as the "Spatial prefetcher"
It is pretty easy to miss, given it's only afforded a single sentence. It's possible to disable it on a per-core basis: https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors On Mon, 29 May 2017 at 16:54, Martin Thompson <[email protected]> wrote: > Switching topics slightly, prefetch extending the effective cache line >> size was causing us some consternation, since we were never able to find >> where it was documented. Do you have a reference to it? When did it start >> happening? >> >> >> It seems like it invalidates all software that was carefully written to >> honor 64 byte cache lines. >> >> >> IIRC Pentium 4 had 128 byte "sectors", but it was never fully explained >> what these were, and the word died with the P4. >> > > I've seen adjacent cacheline prefetching on Intel processors since the > Netburst days (well over a decade). Until Sandy bridge it was generally > recommended to disable them because memory bandwidth often became an issue. > These days it works on the L2 cache sitting along side a prefetcher that > looks for patterns of cache line accesses. L1 has different prefetchers. It > does have quite a noticeable effect on false sharing but not as much as > when within the same 64 byte cache line. > > -- > You received this message because you are subscribed to the Google Groups > "mechanical-sympathy" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > For more options, visit https://groups.google.com/d/optout. > -- You received this message because you are subscribed to the Google Groups "mechanical-sympathy" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
