> And in your below output, as someone had mentioned, pni is sse3.[2]
Yes, it makes sense. Thanks!

>• CPUID Fn0000_0001_ECX[SSE41]: Added.

>• CPUID Fn0000_0001_ECX[SSSE3]: Added.
My understanding is that having bits defined in CPUID and building a CPU
with that feature is different story, maybe definitions in CPUID is for
software to detect CPU capability only but they don't get set yet. I checked
a few new AMD CPU information from www.amd.com and couldn't find one support
them.

If AMD engineer is tracking this email thread, probably he can help clarify.

However, I don't think whether this is true or not makes much difference.
I'd like to know how MeeGo is compiled and what flags are enabled exactly.

After I checked a few source rpm, I still can't tell. Probably I need to
build some to figure out, but I suspect it may be different for various
pkgs.

Thanks!
JD Zheng

On Tue, Apr 6, 2010 at 7:10 PM, Zhang, Austin <[email protected]>wrote:

>  Hi, JD,
>
>
>
> See link [1], page 5:
>
> • CPUID Fn0000_0001_ECX[SSE41]: Added.
>
> • CPUID Fn0000_0001_ECX[SSSE3]: Added.
>
>
>
> And in your below output, as someone had mentioned, pni is sse3.[2]
>
>
>
> [1] http://xtreview.com/images/25481.pdf
>
> [2] http://en.wikipedia.org/wiki/SSE3
>
>
>
> *From:* ezjd [mailto:[email protected]]
> *Sent:* Wednesday, April 07, 2010 3:36 AM
> *To:* Zhang, Austin
> *Cc:* Skyles, Greg S; [email protected]
> *Subject:* Re: [MeeGo-dev] CPU Architectures (was Re: Build for a standard
> PC)
>
>
>
> Here is cpuinfo of my AMD PC, it doesn't have S^3E3 but suprisingly I can't
> find sse3 as well while it should have. And it runs MeeGo image in VBox.
>
>
>
> Anything I get by googling says AMD doesn't have S^3E3, well, I can't
> verify that.
>
>
>
> processor       : 0
>
> vendor_id       : AuthenticAMD
>
> cpu family      : 15
>
> model           : 107
>
> model name      : AMD Athlon(tm) 64 X2 Dual Core Processor 4000+
>
> stepping        : 1
>
> cpu MHz         : 1000.000
>
> cache size      : 512 KB
>
> physical id     : 0
>
> siblings        : 2
>
> core id         : 0
>
> cpu cores       : 2
>
> apicid          : 0
>
> initial apicid  : 0
>
> fdiv_bug        : no
>
> hlt_bug         : no
>
> f00f_bug        : no
>
> coma_bug        : no
>
> fpu             : yes
>
> fpu_exception   : yes
>
> cpuid level     : 1
>
> wp              : yes
>
> flags           : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov
> pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt rdtscp lm
> 3dnowext 3dnow pni cx16 lahf_lm cmp_legacy svm extapic cr8_legacy
> 3dnowprefetch
>
> bogomips        : 2008.99
>
> clflush size    : 64
>
> cache_alignment : 64
>
> address sizes   : 40 bits physical, 48 bits virtual
>
> power management: ts fid vid ttp tm stc 100mhzsteps
>
>
>
>
>
> On Tue, Apr 6, 2010 at 8:51 AM, Zhang, Austin <[email protected]>
> wrote:
>
> From some specific version, AMD processor support ssse3, so please double
> check the output of /proc/cpuinfo for your processor.
>
>
>
> And in fact, AMD processor support not only ssse3, but even sse4.1.
>
>
>
> *From:* [email protected] [mailto:[email protected]] *On
> Behalf Of *ezjd
> *Sent:* Tuesday, April 06, 2010 11:22 PM
> *To:* Skyles, Greg S
> *Cc:* [email protected]
> *Subject:* Re: [MeeGo-dev] CPU Architectures (was Re: Build for a standard
> PC)
>
>
>
> > Note that it's S^3E3 you are looking for, not S^2E3.  Perhaps not the
> most brilliant naming scheme Intel has come up with...
>
> I am not a CPU expert but I think it is SSE3 made the difference in my
> case: image worked in Athlon64X2 while it didn't in Pentium-M.
>
>
>
> According to http://en.wikipedia.org/wiki/SSSE3, SSSE3 doesn't make to AMD
> chips.
>
> > How does the performance balance out across the architectures if this is
> a generic OS ?
>
>
>
> I don't know how to do test but found http://www.anandtech.com/show/1618, 
> obviously it
> didn't test Inter CPU esp. Atom.
>
> Does it make much difference?
>
>
>
> >If ATOM benefits so heavily from SSSE3 instructions, how does ARM keep
> up.
>
>
>
> ARM is RISC so that it doesn't provide more and more instructions for some
> purposes like CISC chip. According to my experience, armv5 is good enough
> for most ARM chip with very good backward compatibility and VFP boosts the
> performance for floating point operation like 3D.
>
>
>
> Thanks.
>
> JD Zheng
>
>
>
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