From: Li Peng <[email protected]> Use gfx core frequency rather than sku to identify different H/W model, It is more clear for people.
Change-Id: Icae06d54efc9d3369de930f3c57d40a2a317567f Signed-off-by: Li Peng <[email protected]> Signed-off-by: Justin Dou <[email protected]> --- drivers/staging/mrst/drv/psb_bl.c | 9 +----- drivers/staging/mrst/drv/psb_drv.c | 14 +++----- drivers/staging/mrst/drv/psb_drv.h | 5 +-- drivers/staging/mrst/drv/psb_intel_display.c | 18 +++++----- drivers/staging/mrst/drv/psb_intel_display2.c | 15 +++++--- drivers/staging/mrst/drv/psb_intel_dsi.c | 42 ++++++++++++++++-------- drivers/staging/mrst/drv/psb_intel_dsi2.c | 23 ++++++------- 7 files changed, 65 insertions(+), 61 deletions(-) diff --git a/drivers/staging/mrst/drv/psb_bl.c b/drivers/staging/mrst/drv/psb_bl.c index 302674e..3095edc 100644 --- a/drivers/staging/mrst/drv/psb_bl.c +++ b/drivers/staging/mrst/drv/psb_bl.c @@ -166,14 +166,7 @@ int psb_backlight_init(struct drm_device *dev) blc_pol = BLC_POLARITY_NORMAL; blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR; - if (dev_priv->sku_83) - CoreClock = 166; - else if (dev_priv->sku_100) - CoreClock = 200; - else if (dev_priv->sku_100L) - CoreClock = 100; - else - return 1; + CoreClock = dev_priv->core_freq; } else { /* get bl_max_freq and pol from dev_priv*/ if (!dev_priv->lvds_bl) { diff --git a/drivers/staging/mrst/drv/psb_drv.c b/drivers/staging/mrst/drv/psb_drv.c index 1cf3570..ad17a09 100644 --- a/drivers/staging/mrst/drv/psb_drv.c +++ b/drivers/staging/mrst/drv/psb_drv.c @@ -627,21 +627,19 @@ void mrst_get_fuse_settings(struct drm_device *dev) switch (fuse_value_tmp) { case FB_SKU_100: - DRM_INFO("SKU values is SKU_100. LNC core clk is 200MHz.\n"); - dev_priv->sku_100 = true; + dev_priv->core_freq = 200; break; case FB_SKU_100L: - DRM_INFO("SKU values is SKU_100L. LNC core clk is 100MHz.\n"); - dev_priv->sku_100L = true; + dev_priv->core_freq = 100; break; case FB_SKU_83: - DRM_INFO("SKU values is SKU_83. LNC core clk is 166MHz.\n"); - dev_priv->sku_83 = true; + dev_priv->core_freq = 166; break; default: - DRM_ERROR("Invalid SKU values, SKU value = 0x%08x\n", - fuse_value_tmp); + DRM_ERROR("Invalid SKU values, SKU value = 0x%08x\n", fuse_value_tmp); + dev_priv->core_freq = 0; } + DRM_INFO("LNC core clk is %dMHz.\n", dev_priv->core_freq); #if 1 /* FIXME remove it after PO */ fuse_value_tmp = diff --git a/drivers/staging/mrst/drv/psb_drv.h b/drivers/staging/mrst/drv/psb_drv.h index f578348..99603cf 100644 --- a/drivers/staging/mrst/drv/psb_drv.h +++ b/drivers/staging/mrst/drv/psb_drv.h @@ -479,10 +479,7 @@ struct drm_psb_private { /* MRST private date start */ /*FIXME JLIU7 need to revisit */ - bool sku_83; - bool sku_100; - bool sku_100L; - bool sku_bypass; + unsigned int core_freq; uint32_t iLVDS_enable; /* pipe config register value */ diff --git a/drivers/staging/mrst/drv/psb_intel_display.c b/drivers/staging/mrst/drv/psb_intel_display.c index 83f3a3e..7b99631 100644 --- a/drivers/staging/mrst/drv/psb_intel_display.c +++ b/drivers/staging/mrst/drv/psb_intel_display.c @@ -1929,12 +1929,17 @@ static const struct mrst_limit_t *mrst_limit(struct drm_crtc *crtc) if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) { - if (dev_priv->sku_100L) + switch (dev_priv->core_freq) { + case 100: limit = &mrst_limits[MRST_LIMIT_LVDS_100L]; - if (dev_priv->sku_83) + break; + case 166: limit = &mrst_limits[MRST_LIMIT_LVDS_83]; - if (dev_priv->sku_100) + break; + case 200: limit = &mrst_limits[MRST_LIMIT_LVDS_100]; + break; + } } else { limit = NULL; PSB_DEBUG_ENTRY("mrst_limit Wrong display type. \n"); @@ -2317,12 +2322,7 @@ static int mrst_crtc_mode_set(struct drm_crtc *crtc, if (is_mipi) goto mrst_crtc_mode_set_exit; - if (dev_priv->sku_100L) - refclk = 100000; - else if (dev_priv->sku_83) - refclk = 166000; - else if (dev_priv->sku_100) - refclk = 200000; + refclk = dev_priv->core_freq * 1000; dpll = 0; /*BIT16 = 0 for 100MHz reference */ diff --git a/drivers/staging/mrst/drv/psb_intel_display2.c b/drivers/staging/mrst/drv/psb_intel_display2.c index 7219a74..b2a57af 100644 --- a/drivers/staging/mrst/drv/psb_intel_display2.c +++ b/drivers/staging/mrst/drv/psb_intel_display2.c @@ -904,18 +904,20 @@ static const struct mrst_limit_t *mdfld_limit(struct drm_crtc *crtc) limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_19]; else if (dev_priv->ksel == KSEL_BYPASS_25) limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_25]; - else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && dev_priv->sku_83) + else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && (dev_priv->core_freq == 166)) limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_83]; - else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && (dev_priv->sku_100L || dev_priv->sku_100)) + else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && + (dev_priv->core_freq == 100 || dev_priv->core_freq == 200)) limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_100]; } else if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { if ((dev_priv->ksel == KSEL_CRYSTAL_19) || (dev_priv->ksel == KSEL_BYPASS_19)) limit = &mdfld_limits[MDFLD_LIMT_DPLL_19]; else if (dev_priv->ksel == KSEL_BYPASS_25) limit = &mdfld_limits[MDFLD_LIMT_DPLL_25]; - else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && dev_priv->sku_83) + else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && (dev_priv->core_freq == 166)) limit = &mdfld_limits[MDFLD_LIMT_DPLL_83]; - else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && (dev_priv->sku_100L || dev_priv->sku_100)) + else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && + (dev_priv->core_freq == 100 || dev_priv->core_freq == 200)) limit = &mdfld_limits[MDFLD_LIMT_DPLL_100]; } else { limit = NULL; @@ -1222,7 +1224,7 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, } else if (is_hdmi) { clk_n = 1, clk_p2 = 10; } - } else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && dev_priv->sku_83) { + } else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && (dev_priv->core_freq == 166)) { refclk = 83000; if (is_mipi || is_mipi2) @@ -1231,7 +1233,8 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, } else if (is_hdmi) { clk_n = 4, clk_p2 = 10; } - } else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && (dev_priv->sku_100L || dev_priv->sku_100)) { + } else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && + (dev_priv->core_freq == 100 || dev_priv->core_freq == 200)) { refclk = 100000; if (is_mipi || is_mipi2) { diff --git a/drivers/staging/mrst/drv/psb_intel_dsi.c b/drivers/staging/mrst/drv/psb_intel_dsi.c index 860468b..5f5f37b 100644 --- a/drivers/staging/mrst/drv/psb_intel_dsi.c +++ b/drivers/staging/mrst/drv/psb_intel_dsi.c @@ -1123,13 +1123,16 @@ void mrst_init_NSC_MIPI_bridge(struct drm_device *dev) REG_WRITE(LP_GEN_CTRL_REG, 0x00007de3); mrst_wait_for_LP_CTRL_FIFO(dev); - if (dev_priv->sku_83) { - /* set escape clock to divede by 8 */ - REG_WRITE(LP_GEN_CTRL_REG, 0x000044e3); - } else if (dev_priv->sku_100L) { + switch (dev_priv->core_freq) { + case 100: /* set escape clock to divede by 16 */ REG_WRITE(LP_GEN_CTRL_REG, 0x001044e3); - } else if (dev_priv->sku_100) { + break; + case 166: + /* set escape clock to divede by 8 */ + REG_WRITE(LP_GEN_CTRL_REG, 0x000044e3); + break; + case 200: /* set escape clock to divede by 32*/ /*REG_WRITE(LP_GEN_CTRL_REG, 0x003044e3);*/ REG_WRITE(LP_GEN_CTRL_REG, 0x001044e3); @@ -1137,6 +1140,7 @@ void mrst_init_NSC_MIPI_bridge(struct drm_device *dev) /*mrst_wait_for_LP_CTRL_FIFO(dev);*/ /* setle = 6h; low power timeout = ((2^21)-1)*4TX_esc_clks. */ /*REG_WRITE(LP_GEN_CTRL_REG, 0x00ec45e3);*/ + break; } mrst_wait_for_LP_CTRL_FIFO(dev); @@ -1741,13 +1745,18 @@ static void mrst_dsi_mode_set(struct drm_encoder *encoder, break; } - /* set 100 mhz dsi clk based on sku */ - if (dev_priv->sku_83) - mipi_control_val = 0x0018; /* 100 mhz * 1 = 100 mhz */ - else if (dev_priv->sku_100L) + /* set 100 mhz dsi clk based on gfx core freq */ + switch (dev_priv->core_freq) { + case 100: mipi_control_val = 0x0019; /* 50 mhz * 2 = 100 mhz */ - else if (dev_priv->sku_100) + break; + case 166: + mipi_control_val = 0x0018; /* 100 mhz * 1 = 100 mhz */ + break; + case 200: mipi_control_val = 0x0018; /* 100 mhz * 1 = 100 mhz */ + break; + } /* wait for PIPE A to disable */ mrst_wait_for_PIPEA_DISABLE(dev); @@ -2100,12 +2109,17 @@ static bool mrstDSI_clockInit(DRM_DRIVER_PRIVATE_T *dev_priv) PSB_DEBUG_ENTRY("mrstDSI_clockInit RRate = %d, mipi_2xclk = %d. \n", RRate, mipi_2xclk); - if (dev_priv->sku_100) - p_mipi_2xclk = sku_100_mipi_2xclk; - else if (dev_priv->sku_100L) + switch (dev_priv->core_freq) { + case 100: p_mipi_2xclk = sku_100L_mipi_2xclk; - else + break; + case 166: p_mipi_2xclk = sku_83_mipi_2xclk; + break; + case 200: + p_mipi_2xclk = sku_100_mipi_2xclk; + break; + } for (; i < MIPI_2XCLK_COUNT; i++) { if ((dev_priv->DDR_Clock_Calculated * 2) < p_mipi_2xclk[i]) diff --git a/drivers/staging/mrst/drv/psb_intel_dsi2.c b/drivers/staging/mrst/drv/psb_intel_dsi2.c index 3b63e1b..6ec1b53 100644 --- a/drivers/staging/mrst/drv/psb_intel_dsi2.c +++ b/drivers/staging/mrst/drv/psb_intel_dsi2.c @@ -3148,18 +3148,17 @@ static bool mdfldDSI_clockInit(DRM_DRIVER_PRIVATE_T *dev_priv, int dsi_num) PSB_DEBUG_ENTRY("RRate = %d, mipi_2xclk = %d. \n", RRate, mipi_2xclk); - if (dev_priv->sku_100) - { - p_mipi_2xclk = mdfld_sku_100_mipi_2xclk; - } - else if (dev_priv->sku_100L) - { - p_mipi_2xclk = mdfld_sku_100L_mipi_2xclk; - } - else - { - p_mipi_2xclk = mdfld_sku_83_mipi_2xclk; - } + switch (dev_priv->core_freq) { + case 100: + p_mipi_2xclk = mdfld_sku_100L_mipi_2xclk; + break; + case 166: + p_mipi_2xclk = mdfld_sku_83_mipi_2xclk; + break; + case 200: + p_mipi_2xclk = mdfld_sku_100_mipi_2xclk; + break; + } for (; i < MDFLD_MIPI_2XCLK_COUNT; i++) { -- 1.7.1 _______________________________________________ MeeGo-kernel mailing list [email protected] http://lists.meego.com/listinfo/meego-kernel
