From: Li Zeng <[email protected]> Add support for DE2.0 Firmware changes.
Change-Id: I6bbb4ffd3f4b1c1ba296dbd7bfda24900810a2ea Signed-off-by: Hitesh K. Patel <[email protected]> --- drivers/staging/mrst/drv/psb_drv.c | 8 ++- drivers/staging/mrst/imgv/psb_msvdx.c | 88 ++++++++++++++++++++++++---- drivers/staging/mrst/imgv/psb_msvdx.h | 78 +++++++++++++++++++++++++- drivers/staging/mrst/imgv/psb_msvdxinit.c | 16 ++++- 4 files changed, 171 insertions(+), 19 deletions(-) diff --git a/drivers/staging/mrst/drv/psb_drv.c b/drivers/staging/mrst/drv/psb_drv.c index 3624152..6aa1baa 100644 --- a/drivers/staging/mrst/drv/psb_drv.c +++ b/drivers/staging/mrst/drv/psb_drv.c @@ -1178,7 +1178,6 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset) if (IS_TOPAZ(dev)) { if(IS_MDFLD(dev)) { - printk("map topazSC register space\n"); dev_priv->topaz_reg = ioremap(resource_start + PNW_TOPAZ_OFFSET, PNW_TOPAZ_SIZE); @@ -1229,6 +1228,13 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset) if (unlikely(ret != 0)) goto out_err; + /* For VXD385 DE2.x firmware support 16bit fence value */ + if(IS_MDFLD(dev) && IS_FW_UPDATED) { + dev_priv->fdev.fence_class[PSB_ENGINE_VIDEO].wrap_diff = (1 << 14); + dev_priv->fdev.fence_class[PSB_ENGINE_VIDEO].flush_diff = ( 1 << 13); + dev_priv->fdev.fence_class[PSB_ENGINE_VIDEO].sequence_mask = 0x0000ffff; + } + dev_priv->has_fence_device = 1; ret = ttm_bo_device_init(bdev, dev_priv->bo_global_ref.ref.object, diff --git a/drivers/staging/mrst/imgv/psb_msvdx.c b/drivers/staging/mrst/imgv/psb_msvdx.c index bedbd5f..70a62b7 100644 --- a/drivers/staging/mrst/imgv/psb_msvdx.c +++ b/drivers/staging/mrst/imgv/psb_msvdx.c @@ -113,19 +113,36 @@ static int psb_msvdx_map_command(struct drm_device *dev, switch (cur_cmd_id) { case VA_MSGID_RENDER: /* Fence ID */ - MEMIO_WRITE_FIELD(cmd, FW_VA_RENDER_FENCE_VALUE, - sequence); + if(IS_MDFLD(dev) && IS_FW_UPDATED) + MEMIO_WRITE_FIELD(cmd, FW_VA_DECODE_MSG_ID, sequence); + else + MEMIO_WRITE_FIELD(cmd, FW_VA_RENDER_FENCE_VALUE, sequence); + mmu_ptd = psb_get_default_pd_addr(dev_priv->mmu); tmp = atomic_cmpxchg(&dev_priv->msvdx_mmu_invaldc, 1, 0); if (tmp == 1) { - mmu_ptd |= 1; + if(!(IS_MDFLD(dev) && IS_FW_UPDATED)) + mmu_ptd |= 1; + else { + uint32_t flags; + flags = MEMIO_READ_FIELD(cmd, FW_DEVA_DECODE_FLAGS); + flags |= FW_DEVA_INVALIDATE_MMU; + MEMIO_WRITE_FIELD(cmd, FW_DEVA_DECODE_FLAGS, flags); + } + PSB_DEBUG_GENERAL("MSVDX:Set MMU invalidate\n"); } /* PTD */ - MEMIO_WRITE_FIELD(cmd, FW_VA_RENDER_MMUPTD, mmu_ptd); - + if(IS_MDFLD(dev) && IS_FW_UPDATED) { + uint32_t context_id; + context_id = MEMIO_READ_FIELD(cmd, FW_VA_DECODE_MMUPTD); + mmu_ptd = mmu_ptd | (context_id & 0xff); + MEMIO_WRITE_FIELD(cmd, FW_VA_DECODE_MMUPTD, mmu_ptd); + } + else + MEMIO_WRITE_FIELD(cmd, FW_VA_RENDER_MMUPTD, mmu_ptd); break; case DXVA_MSGID_OOLD: @@ -146,6 +163,33 @@ static int psb_msvdx_map_command(struct drm_device *dev, break; + case VA_MSGID_DEBLOCK_MFLD: { + FW_VA_DEBLOCK_MSG * deblock_msg; + + PSB_DEBUG_GENERAL("MSVDX:Get deblock cmd for medfield\n"); + + deblock_msg = (FW_VA_DEBLOCK_MSG*)cmd; + + mmu_ptd = psb_get_default_pd_addr(dev_priv->mmu); + tmp = atomic_cmpxchg(&dev_priv->msvdx_mmu_invaldc, + 1, 0); + if (tmp == 1) { + uint32_t flags; + flags = deblock_msg->flags; + flags |= FW_DEVA_INVALIDATE_MMU; + deblock_msg->flags = flags; + + PSB_DEBUG_GENERAL("MSVDX:Set MMU invalidate\n"); + } + + + deblock_msg->header.bits.msg_type = VA_MSGID_DEBLOCK; /* patch to right cmd type */ + deblock_msg->header.bits.msg_fence = (uint16_t)(sequence & 0xffff); + deblock_msg->mmu_context.bits.mmu_ptd = (mmu_ptd >> 8); + + } + break; + case VA_MSGID_DEBLOCK: /* Fence ID */ MEMIO_WRITE_FIELD(cmd, FW_DXVA_DEBLOCK_FENCE_VALUE, @@ -416,7 +460,7 @@ static int psb_msvdx_send(struct drm_device *dev, void *cmd, } cmd += cur_cmd_size; cmd_size -= cur_cmd_size; - if (cur_cmd_id == VA_MSGID_DEBLOCK) { + if (cur_cmd_id == VA_MSGID_DEBLOCK && !(IS_MDFLD(dev) && IS_FW_UPDATED)) { cmd += 32; cmd_size -= 32; } @@ -441,6 +485,16 @@ int psb_mtx_send(struct drm_psb_private *dev_priv, const void *msg) msg_num = (MEMIO_READ_FIELD(msg, FWRK_GENMSG_SIZE) + 3) / 4; +/* + { + int i; + printk("MSVDX: psb_mtx_send is %dDW\n", msg_num); + + for(i = 0; i < msg_num; i++) + printk("0x%08x ", p_msg[i]); + printk("\n"); + } +*/ buf_size = PSB_RMSVDX32(MSVDX_COMMS_TO_MTX_BUF_SIZE) & ((1 << 16) - 1); if (msg_num > buf_size) { @@ -489,9 +543,9 @@ int psb_mtx_send(struct drm_psb_private *dev_priv, const void *msg) } if (widx >= ridx) - words_free = buf_size - (widx - ridx); + words_free = buf_size - (widx - ridx) - 1; else - words_free = ridx - widx; + words_free = ridx - widx - 1; BUG_ON(msg_num > words_free); if (msg_num > words_free) { @@ -673,7 +727,6 @@ loop: /* just for coding style check */ goto loop; switch (MEMIO_READ_FIELD(buf, FWRK_GENMSG_ID)) { - /* FIXME error recovery handle is not implement yet! Need to queue pending msg for error recovery */ case VA_MSGID_CMD_HW_PANIC: case VA_MSGID_CMD_FAILED: { /* For VXD385 firmware, fence value is not validate here */ @@ -685,6 +738,12 @@ loop: /* just for coding style check */ uint32_t diff = 0; (void) fault; + + if(IS_MDFLD(dev) && IS_FW_UPDATED) { + fence = MEMIO_READ_FIELD(buf, FW_DEVA_CMD_FAILED_MSG_ID); + fault = MEMIO_READ_FIELD(buf, FW_DEVA_CMD_FAILED_FLAGS); + } + if (msg_id == VA_MSGID_CMD_HW_PANIC) PSB_DEBUG_GENERAL("MSVDX: VA_MSGID_CMD_HW_PANIC:" "Fault detected" @@ -724,10 +783,13 @@ loop: /* just for coding style check */ goto done; } case VA_MSGID_CMD_COMPLETED: { - uint32_t fence = MEMIO_READ_FIELD(buf, - FW_VA_CMD_COMPLETED_FENCE_VALUE); - uint32_t flags = MEMIO_READ_FIELD(buf, - FW_VA_CMD_COMPLETED_FLAGS); + uint32_t fence; + uint32_t flags = MEMIO_READ_FIELD(buf, FW_VA_CMD_COMPLETED_FLAGS); + + if(IS_MDFLD(dev) && IS_FW_UPDATED) + fence = MEMIO_READ_FIELD(buf, FW_VA_CMD_COMPLETED_MSG_ID); + else + fence = MEMIO_READ_FIELD(buf, FW_VA_CMD_COMPLETED_FENCE_VALUE); PSB_DEBUG_GENERAL("MSVDX:VA_MSGID_CMD_COMPLETED: " "FenceID: %08x, flags: 0x%x\n", diff --git a/drivers/staging/mrst/imgv/psb_msvdx.h b/drivers/staging/mrst/imgv/psb_msvdx.h index fc83f93..91cb277 100644 --- a/drivers/staging/mrst/imgv/psb_msvdx.h +++ b/drivers/staging/mrst/imgv/psb_msvdx.h @@ -198,7 +198,7 @@ MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET_MASK) (*((field##_TYPE*)(((uint32_t)vpMem) + field##_OFFSET))) = \ ((*((field##_TYPE*)(((uint32_t)vpMem) + field##_OFFSET))) \ & (field##_TYPE)~field##_MASK) | \ - (field##_TYPE)(((uint32_t)(value) << field##_SHIFT) & field##_MASK); + (field##_TYPE)(((uint32_t)(value) << field##_SHIFT) & field##_MASK) #define MEMIO_WRITE_FIELD_LITE(vpMem, field, value) \ (*((field##_TYPE*)(((uint32_t)vpMem) + field##_OFFSET))) = \ @@ -484,6 +484,9 @@ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_MASK) /* Start of parser specific MTX->Host messages. */ #define FWRK_MSGID_START_PSR_MTXHOST_MSG (0xC0) +/* Host defined msg, just for host use, MTX not recgnize */ +#define FWRK_MSGID_HOST_EMULATED (0x40) + #define FWRK_MSGID_PADDING (0) #define FWRK_GENMSG_SIZE_TYPE uint8_t @@ -523,6 +526,7 @@ enum { */ VA_MSGID_RENDER_MC_INTERRUPT, + VA_MSGID_DEBLOCK_MFLD = FWRK_MSGID_HOST_EMULATED, /*! Sent by the DXVA firmware on the MTX to the host. */ VA_MSGID_CMD_COMPLETED = FWRK_MSGID_START_PSR_MTXHOST_MSG, @@ -553,6 +557,39 @@ struct psb_msvdx_deblock_queue { struct DEBLOCKPARAMS dbParams; }; +typedef struct { + union { + struct { + uint32_t msg_size : 8; + uint32_t msg_type : 8; + uint32_t msg_fence : 16; + } bits; + uint32_t value; + } header; + uint32_t flags; + uint32_t operating_mode; + union { + struct { + uint32_t context : 8; + uint32_t mmu_ptd : 24; + } bits; + uint32_t value; + } mmu_context; + union { + struct { + uint32_t frame_height_mb : 16; + uint32_t pic_width_mb : 16; + } bits; + uint32_t value; + } pic_size; + uint32_t address_a0; + uint32_t address_a1; + uint32_t mb_param_address; + uint32_t address_b0; + uint32_t address_b1; + uint32_t rotation_flags; +} FW_VA_DEBLOCK_MSG; + /* MSVDX private structure */ struct msvdx_private { int msvdx_needs_reset; @@ -688,6 +725,43 @@ struct msvdx_private { #define FW_VA_RENDER_FLAGS_OFFSET (0x001C) #define FW_VA_RENDER_FLAGS_SHIFT (0) +/* FW_DEVA_DECODE MMUPTD */ +#define FW_VA_DECODE_MMUPTD_TYPE uint32_t +#define FW_VA_DECODE_MMUPTD_MASK (0xFFFFFF00) +#define FW_VA_DECODE_MMUPTD_OFFSET (0x000C) +#define FW_VA_DECODE_MMUPTD_SHIFT (0) + +/* FW_DEVA_DECODE MSG_ID */ +#define FW_VA_DECODE_MSG_ID_TYPE uint16_t +#define FW_VA_DECODE_MSG_ID_MASK (0xFFFF) +#define FW_VA_DECODE_MSG_ID_OFFSET (0x0002) +#define FW_VA_DECODE_MSG_ID_SHIFT (0) + +/* FW_DEVA_DECODE FLAGS */ +#define FW_DEVA_DECODE_FLAGS_TYPE uint16_t +#define FW_DEVA_DECODE_FLAGS_MASK (0xFFFF) +#define FW_DEVA_DECODE_FLAGS_OFFSET (0x0004) +#define FW_DEVA_DECODE_FLAGS_SHIFT (0) + +#define FW_DEVA_INVALIDATE_MMU (0x00000010) + +/* FW_DEVA_CMD_COMPLETED MSG_ID */ +#define FW_VA_CMD_COMPLETED_MSG_ID_TYPE uint16_t +#define FW_VA_CMD_COMPLETED_MSG_ID_MASK (0xFFFF) +#define FW_VA_CMD_COMPLETED_MSG_ID_OFFSET (0x0002) +#define FW_VA_CMD_COMPLETED_MSG_ID_SHIFT (0) + +/* FW_DEVA_CMD_FAILED MSG_ID */ +#define FW_DEVA_CMD_FAILED_MSG_ID_TYPE uint16_t +#define FW_DEVA_CMD_FAILED_MSG_ID_MASK (0xFFFF) +#define FW_DEVA_CMD_FAILED_MSG_ID_OFFSET (0x0002) +#define FW_DEVA_CMD_FAILED_MSG_ID_SHIFT (0) + +/* FW_DEVA_CMD_FAILED FLAGS */ +#define FW_DEVA_CMD_FAILED_FLAGS_TYPE uint32_t +#define FW_DEVA_CMD_FAILED_FLAGS_MASK (0xFFFFFFFF) +#define FW_DEVA_CMD_FAILED_FLAGS_OFFSET (0x0004) +#define FW_DEVA_CMD_FAILED_FLAGS_SHIFT (0) /* FW_DXVA_DEBLOCK MSG_SIZE */ #define FW_DXVA_DEBLOCK_MSG_SIZE_ALIGNMENT (1) @@ -783,3 +857,5 @@ do { \ } while (0) #endif + +#define IS_FW_UPDATED 1 diff --git a/drivers/staging/mrst/imgv/psb_msvdxinit.c b/drivers/staging/mrst/imgv/psb_msvdxinit.c index ccce934..4dae367 100644 --- a/drivers/staging/mrst/imgv/psb_msvdxinit.c +++ b/drivers/staging/mrst/imgv/psb_msvdxinit.c @@ -551,8 +551,12 @@ int psb_setup_fw(struct drm_device *dev) PSB_DEBUG_GENERAL("MSVDX:load msvdx_fw.bin by udevd\n"); } else if (IS_MDFLD(dev)) { - fw_ptr = msvdx_get_fw(dev, &raw, "msvdx_fw_mfld.bin"); - PSB_DEBUG_GENERAL("MSVDX:load msvdx_fw_mfld.bin by udevd\n"); + if(IS_FW_UPDATED) + fw_ptr = msvdx_get_fw(dev, &raw, "msvdx_fw_mfld_DE2.0.bin"); + else + fw_ptr = msvdx_get_fw(dev, &raw, "msvdx_fw_mfld.bin"); + + PSB_DEBUG_GENERAL("MSVDX:load msvdx_fw_mfld_DE2.0.bin by udevd\n"); } else DRM_ERROR("MSVDX:HW is neither mrst nor mfld\n"); @@ -568,8 +572,12 @@ int psb_setup_fw(struct drm_device *dev) PSB_DEBUG_GENERAL("MSVDX:load msvdx_fw.bin by udevd into BO\n"); if(IS_MRST(dev)) ret = msvdx_get_fw_bo(dev, &raw, "msvdx_fw.bin"); - else if(IS_MDFLD(dev)) - ret = msvdx_get_fw_bo(dev, &raw, "msvdx_fw_mfld.bin"); + else if(IS_MDFLD(dev)) { + if(IS_FW_UPDATED) + ret = msvdx_get_fw_bo(dev, &raw, "msvdx_fw_mfld_DE2.0.bin"); + else + ret = msvdx_get_fw_bo(dev, &raw, "msvdx_fw_mfld.bin"); + } else DRM_ERROR("MSVDX:HW is neither mrst nor mfld\n"); msvdx_priv->is_load = 1; -- 1.7.1 _______________________________________________ MeeGo-kernel mailing list [email protected] http://lists.meego.com/listinfo/meego-kernel
