From: Hitesh K. Patel <[email protected]>

Fix for a couple of Klocwork array index out of bounds issues.
Remove hard-coded size in the for-loop in favour of looping
on the size of the array.  Also, ensure that all arrays are
integral sizes of u32 entries.

Signed-off-by: Steve Aarnio <[email protected]>
Signed-off-by: Hitesh K. Patel <[email protected]>
---
 drivers/staging/mrst/drv/mdfld_dsi_output.c |   59 +++++++++++++++++---------
 drivers/staging/mrst/drv/psb_drv.c          |    5 +--
 2 files changed, 39 insertions(+), 25 deletions(-)

diff --git a/drivers/staging/mrst/drv/mdfld_dsi_output.c 
b/drivers/staging/mrst/drv/mdfld_dsi_output.c
index 033be2f..42c7b17 100644
--- a/drivers/staging/mrst/drv/mdfld_dsi_output.c
+++ b/drivers/staging/mrst/drv/mdfld_dsi_output.c
@@ -82,27 +82,28 @@ early_param ("LABC", parse_LABC_control);
  **/
 static const u8 mdfld_dbi_mcs_hysteresis[] = { 
        0x57, /*MCS write_hysteresis*/
-       0x0f, 0x00, 0x42, 0x00,
-       0x64, 0x00, 0x8c, 0x00,
-       0xbf, 0x00, 0xff, 0xff,
+                 0x0f, 0x00, 0x42,
+       0x00, 0x64, 0x00, 0x8c,
+       0x00, 0xbf, 0x00, 0xff,
        0xff, 0xff, 0xff, 0xff,
        0xff, 0xff, 0xff, 0xff,
        0xff, 0xff, 0xff, 0xff,
        0xff, 0xff, 0xff, 0xff,
        0xff, 0xff, 0xff, 0xff,
-       0x0a, 0x00, 0x38, 0x00,
-       0x50, 0x00, 0x82, 0x00,
-       0xab, 0x00, 0xff, 0xff,
+       0xff, 0x0a, 0x00, 0x38,
+       0x00, 0x50, 0x00, 0x82,
+       0x00, 0xab, 0x00, 0xff,
        0xff, 0xff, 0xff, 0xff,
        0xff, 0xff, 0xff, 0xff,
        0xff, 0xff, 0xff, 0xff,
        0xff, 0xff, 0xff, 0xff,
        0xff, 0xff, 0xff, 0xff,
+       0xff, 0x00, 0x00, 0x00
 };
 
 static const u8 mdfld_dbi_mcs_display_profile[] = {    
        0x50, /*MCS write_display_profile*/     
-       0x14, 0x28, 0x50,
+                 0x14, 0x28, 0x50,
        0x82, 0xc8, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00,
@@ -111,7 +112,7 @@ static const u8 mdfld_dbi_mcs_display_profile[] = {
 
 static const u8 mdfld_dbi_mcs_kbbc_profile[] = {
        0x60, /*MCS write_kbbc_profile*/        
-       0xcc, 0xff, 0x00,
+                 0xcc, 0xff, 0x00,
        0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00,
@@ -119,7 +120,7 @@ static const u8 mdfld_dbi_mcs_kbbc_profile[] = {
        
 static const u8 mdfld_dbi_mcs_gamma_profile[] = {
        0x58, /*MCS write_gamma_setting*/       
-       0x11, 0x11, 0x81,
+                 0x11, 0x11, 0x81,
        0x88, 0x88, 0x88, 0x88,
        0x88, 0x88, 0x88, 0x88,
 }; 
@@ -133,9 +134,9 @@ static void mdfld_dsi_write_hysteresis (struct 
mdfld_dsi_config * dsi_config, in
        u32 hs_gen_data_reg = MIPIA_HS_GEN_DATA_REG; 
        u32 hs_gen_ctrl_reg = MIPIA_HS_GEN_CTRL_REG;
        u32 *p_gen_data_val = 0;
+       u32 *p_gen_data_val_last = 0;
        u32 gen_ctrl_val = 0;
        u32 dcsChannelNumber = dsi_config->channel_num;
-       u32 i = 0;
 
        if (pipe == 2) {
                hs_gen_data_reg += MIPIC_REG_OFFSET; 
@@ -143,9 +144,13 @@ static void mdfld_dsi_write_hysteresis (struct 
mdfld_dsi_config * dsi_config, in
        }
 
        p_gen_data_val = (u32 *)mdfld_dbi_mcs_hysteresis;
+       p_gen_data_val_last = p_gen_data_val;
+       p_gen_data_val_last +=
+               (ARRAY_SIZE(mdfld_dbi_mcs_hysteresis) / sizeof(u32)) - 1;
 
-       for (i = 0; i < (68 / 4); i++) {
-               REG_WRITE(hs_gen_data_reg, *(p_gen_data_val + i));
+       while (p_gen_data_val <= p_gen_data_val_last) {
+               REG_WRITE(hs_gen_data_reg, *p_gen_data_val);
+               p_gen_data_val++;
        }
 
        gen_ctrl_val = 65 << WORD_COUNTS_POS;
@@ -163,9 +168,9 @@ static void mdfld_dsi_write_display_profile (struct 
mdfld_dsi_config * dsi_confi
        u32 hs_gen_data_reg = MIPIA_HS_GEN_DATA_REG; 
        u32 hs_gen_ctrl_reg = MIPIA_HS_GEN_CTRL_REG;
        u32 *p_gen_data_val = 0;
+       u32 *p_gen_data_val_last = 0;
        u32 gen_ctrl_val = 0;
        u32 dcsChannelNumber = dsi_config->channel_num;
-       u32 i = 0;
 
        if (pipe == 2) {
                hs_gen_data_reg += MIPIC_REG_OFFSET; 
@@ -173,9 +178,13 @@ static void mdfld_dsi_write_display_profile (struct 
mdfld_dsi_config * dsi_confi
        }
 
        p_gen_data_val = (u32 *)mdfld_dbi_mcs_display_profile;
+       p_gen_data_val_last = p_gen_data_val;
+       p_gen_data_val_last +=
+               (ARRAY_SIZE(mdfld_dbi_mcs_display_profile) / sizeof(u32)) - 1;
 
-       for (i = 0; i < (20 / 4); i++) {
-               REG_WRITE(hs_gen_data_reg, *(p_gen_data_val + i));
+       while (p_gen_data_val <= p_gen_data_val_last) {
+               REG_WRITE(hs_gen_data_reg, *p_gen_data_val);
+               p_gen_data_val++;
        }
 
        gen_ctrl_val = 17 << WORD_COUNTS_POS;
@@ -193,9 +202,9 @@ static void mdfld_dsi_write_kbbc_profile (struct 
mdfld_dsi_config * dsi_config,
        u32 hs_gen_data_reg = MIPIA_HS_GEN_DATA_REG; 
        u32 hs_gen_ctrl_reg = MIPIA_HS_GEN_CTRL_REG;
        u32 *p_gen_data_val = 0;
+       u32 *p_gen_data_val_last = 0;
        u32 gen_ctrl_val = 0;
        u32 dcsChannelNumber = dsi_config->channel_num;
-       u32 i = 0;
 
        if (pipe == 2) {
                hs_gen_data_reg += MIPIC_REG_OFFSET; 
@@ -203,9 +212,13 @@ static void mdfld_dsi_write_kbbc_profile (struct 
mdfld_dsi_config * dsi_config,
        }
 
        p_gen_data_val = (u32 *)mdfld_dbi_mcs_kbbc_profile;
+       p_gen_data_val_last = p_gen_data_val;
+       p_gen_data_val_last +=
+               (ARRAY_SIZE(mdfld_dbi_mcs_kbbc_profile) / sizeof(u32)) - 1;
 
-       for (i = 0; i < (20 / 4); i++) {
-               REG_WRITE(hs_gen_data_reg, *(p_gen_data_val + i));
+       while (p_gen_data_val <= p_gen_data_val_last) {
+               REG_WRITE(hs_gen_data_reg, *p_gen_data_val);
+               p_gen_data_val++;
        }
 
        gen_ctrl_val = 17 << WORD_COUNTS_POS;
@@ -223,9 +236,9 @@ static void mdfld_dsi_write_gamma_setting (struct 
mdfld_dsi_config * dsi_config,
        u32 hs_gen_data_reg = MIPIA_HS_GEN_DATA_REG; 
        u32 hs_gen_ctrl_reg = MIPIA_HS_GEN_CTRL_REG;
        u32 *p_gen_data_val = 0;
+       u32 *p_gen_data_val_last = 0;
        u32 gen_ctrl_val = 0;
        u32 dcsChannelNumber = dsi_config->channel_num;
-       u32 i = 0;
 
        if (pipe == 2) {
                hs_gen_data_reg += MIPIC_REG_OFFSET; 
@@ -233,9 +246,13 @@ static void mdfld_dsi_write_gamma_setting (struct 
mdfld_dsi_config * dsi_config,
        }
 
        p_gen_data_val = (u32 *)mdfld_dbi_mcs_gamma_profile;
+       p_gen_data_val_last = p_gen_data_val;
+       p_gen_data_val_last +=
+               (ARRAY_SIZE(mdfld_dbi_mcs_gamma_profile) / sizeof(u32)) - 1;
 
-       for (i = 0; i < (12 / 4); i++) {
-               REG_WRITE(hs_gen_data_reg, *(p_gen_data_val + i));
+       while (p_gen_data_val <= p_gen_data_val_last) {
+               REG_WRITE(hs_gen_data_reg, *p_gen_data_val);
+               p_gen_data_val++;
        }
 
        gen_ctrl_val = 9 << WORD_COUNTS_POS;
diff --git a/drivers/staging/mrst/drv/psb_drv.c 
b/drivers/staging/mrst/drv/psb_drv.c
index 1096864..3954c2c 100644
--- a/drivers/staging/mrst/drv/psb_drv.c
+++ b/drivers/staging/mrst/drv/psb_drv.c
@@ -472,8 +472,6 @@ static struct drm_ioctl_desc psb_ioctls[] = {
                      DRM_AUTH)
 };
 
-static int psb_max_ioctl = DRM_ARRAY_SIZE(psb_ioctls);
-
 static void get_ci_info(struct drm_psb_private *dev_priv)
 {
        struct pci_dev *pdev;
@@ -2770,6 +2768,7 @@ static struct drm_driver driver = {
        .unload = psb_driver_unload,
 
        .ioctls = psb_ioctls,
+       .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
        .device_is_agp = psb_driver_device_is_agp,
        .irq_preinstall = psb_irq_preinstall,
        .irq_postinstall = psb_irq_postinstall,
@@ -2857,8 +2856,6 @@ static int __init psb_init(void)
 {
        int ret;
 
-       driver.num_ioctls = psb_max_ioctl;
-
 #if defined(MODULE) && defined(CONFIG_NET)
        psb_kobject_uevent_init();
 #endif
-- 
1.7.1

_______________________________________________
MeeGo-kernel mailing list
[email protected]
http://lists.meego.com/listinfo/meego-kernel

Reply via email to