From: Yakui <[email protected]> On the MRST platform the HISPD bit should be cleared in order to enable the 50M high-speed clock for SD host controller. But now there exist the two confilcting quirk defitions, which cause that the HISPD bit is not configured correctly. In such case the SD host controller will work in low-speed mode.
Signed-off-by: Zhao Yakui <[email protected]> Signed-off-by: Huang Hang <[email protected]> --- drivers/mmc/host/sdhci-pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Index: linux-2.6.35.3/drivers/mmc/host/sdhci-pci.c =================================================================== --- linux-2.6.35.3.orig/drivers/mmc/host/sdhci-pci.c +++ linux-2.6.35.3/drivers/mmc/host/sdhci-pci.c @@ -169,13 +169,13 @@ static const struct sdhci_pci_fixes sdhc .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_SERIALIZE | SDHCI_QUIRK_BROKEN_RESETALL | - SDHCI_QUIRK_FORCE_FULL_SPEED_MODE, + SDHCI_QUIRK_NO_HISPD_BIT, }; static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1 = { .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_BROKEN_RESETALL | - SDHCI_QUIRK_FORCE_FULL_SPEED_MODE, + SDHCI_QUIRK_NO_HISPD_BIT, .probe = mrst_hc1_probe, }; _______________________________________________ MeeGo-kernel mailing list [email protected] http://lists.meego.com/listinfo/meego-kernel
