RISC was introduced to have a FEW instructions. In the SPARC RISC code you don`t have
the
mov or the cmp instruction. mov is replaced by OR whith 0 or ADD a 0 or
somethings like this. CMP Rx can be replaced by
subcc %Rx,%g0,%g0
where it puts the result to g0, which is always 0, and sets the condition code.
if (a+b>=0)
c=a+b
else
...
can be coded by
addcc a,b,c
bge next1
...
I think if one day there will be a well declared number of jobs which a
processor will have to solve (and this day will come) , then the limits between
RISC and CISC will disappear, because they will have the best possible code to
do that. But as long as the demanded jobs change from year to year CISC
processors will have a blow up to be fully compatible and RISC processors will
have it`s limited instruction code.
And operations like
mov eax,[esi+4*ebx]
have been also implemented in RISC (or in an similar way).
At the moment it becomes to be like a war between religions. But it will
continue as an interessting story.
greetings
Bojan
