>c:=a+b
>RISC: add a,b,c
>CISC: mov a,c (1)
> add b,c (2)
>
>When (2) depends on (1), there is no possibility for parallelization.
>Good, you can argue that instructions on 3 operators are better than
>the one on 2 instructions.
I'm no expert, but isn't this an unfair characterization of CISC? I know
that MIPS uses the "add a,b,c" format and Intel uses "add a,b", but
Intel is just one CISC architecture. I don't see any reason why you
couldn't build a CISC processor with a three-operand format.
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