> Date: Mon, 26 Oct 1998 16:26:54 -0500 (EST)
> From: "Brian U. Peltzer" <[EMAIL PROTECTED]>
> To: Bojan Antonovic <[EMAIL PROTECTED]>
> cc: [EMAIL PROTECTED]
> Subject: Re: Mersenne: AMD K7 will "smoke" Intel FPU?
> MIME-Version: 1.0
>
> On Thu, 22 Oct 1998, Bojan Antonovic wrote:
> <SNIP>
> >
> > c:=a+b
> > RISC: add a,b,c
> > CISC: mov a,c (1)
> > add b,c (2)
> >
> > When (2) depends on (1), there is no possibility for parallelization. Good,
you
> > can argue that instructions on 3 operators are better than the one on 2
> > instructions.
> >
> > Bojan
> >
> >
>
> (1) Ummmm. I hate to be picky, but that code is not the same...
> add b,c; move a,b (just thought is was funny nobody
> mentioned it)
Why ? But it depends on declaration of the execution order (left to right).
> (2) Sure, you loose the parallelism between the two instructions,
> but aren't you forgetting basic pipelining? Simple wrap arounds will make
> that execute in one more cycle than the RISC equivalent. Big deal.
Before doing a branch, the precosser executes the command written after the
branch. So it compensates.
> You
> are also not taking into account that some cisc based routines will take a
> shorter time than some RISC.
No. Speedup is made by loosing some space on the DIE to reach the goal, so this
is independent of the architecture (if you mean that).
> instruction level, you are comparing apples and oranges. I don't even
> think there IS a level ground to actually compare them on.
Why that ? If two things should do the same, why shouldn`t be there a comparison
?
Bojan
