On Sun, 7 Mar 1999 [EMAIL PROTECTED] wrote:
>
> If one were to build a microprocessor SPECIFICALLY suited to LL testing,
> what would the assembly instruction set look like? Approximately what
> would the architecture look like? Speed shouldn't be an issue because
> there's never enough anyway and we're trying to work smarter not harder.
For floating point FFTs: Get all the memory bandwidth you can,
build a large cache, make it non-blocking on a cache miss. Allow
prefetching. Double precision floating point (53-bit IEEE is enough),
superscalar execution, separate pipelined FPU add and multiply units
would be nice. Nothing else is necessary in the FPU, other than
register moves.
For integer FFTs: get yourself a good n-bit to 2n-bit multiply, pipeline
it if you have to but make it real fast. Superscalar is also nice, but
memory bandwidth isn't as important because you can get away with a
smaller array to store the data in.
Making a standard risc ALU instruction set (the 3-operand kind) would
be nice also.
Unfortunately, I just described the UltraSPARC, the Alpha and the PII.
If you *insist* on a do-it-yourself job, look into Analog Devices'
SHARC line of DSP chips, they kick butt for high-bandwidth integer math.
jasonp
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