> [mailto:[EMAIL PROTECTED]]On Behalf Of Terry S. Arnold
> Aaron
>
> You got the resistance part wrong. As the trace gets smaller the
> resistance
> increases because the cross-section of the trace gets smaller.
Doh! Of course you're right. There is a benefit though in having the
traces use shorter runs, even though their width decreases.
FWIW, Intel keeps the resistance of a cross-section *about* the same when
they reduce the width, by making it, erm..."taller" when possible. But I
suspect much of the clock speed increases come from lower voltages also.
Also FWIW, the package of a PII is nothing more than the CPU and a couple of
chips for the L2 cache. It's *possible* that the first Celerons were PII's
with failed L2 cache chips that were then disabled, but not likely. Since
they are seperate chips and are assembled in the package, each chip is
tested prior to packaging and there wouldn't really be any PII's with bad
cache.
If you opened a PII or Celeron cartridge, you'd see that the Celeron
(cacheless) is just plain missing those extra 2 chips. It's not really like
the 486sx which were 486DX chips with the FPU purposely disabled.
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