Just a note of explanation and some (decidedly unofficial) benchmarks:
P6 family processors:
Pentium Pro: The original 6th generation CPU; had 256, 512, or 1024K L2
cache, running at core speed. Bus speed: 60-66MHz; Internal speed: 150-200
MHz.
Pentium II (Klamath): Slightly optimized PPro core with MMX instruction set.
512KB cache running at 1/2 core speed. Bus speed: 66MHz; internal speed:
266-350 MHz. 0.35um process.
Pentium II Xeon: Same core as Klamath; 512, 1024, or 2048KB L2 cache running
at core speed.
Pentium II (Deschutes): Shrink of Klamath onto 0.25um process, minor
optimizations. Bus speed raised to 100MHz, core speed 300 - 450 MHz. Also
in Xeon version.
Mobile PII (Dixon): Uses Deschutes core, speed limited to <350 MHz for
thermal and battery power consumption reasons. Packaged in a much smaller
version of the PII cartridge; uses a pin socket rather than Slot 1.
Pentium III (Katmai): Deschutes + 32MB additional L1 cache + new MMX (KNI)
instruction set. Speed up to 550 MHz (for now). Also in Xeon version.
Upcoming PIII (Coppermine): Katmai core shrunk onto 0.18um process;
additional optimizations, and on die L2 cache >= 256KB, depending on
version. Supposed to be introduced at core speeds of >= 600 MHz; bus speed
of 100 or 133 MHz.
Relative timings at equivalent core speeds for Prime95:
Baseline: Pentium II = 1; 384K FFT size.
PII Xeon: 512KB = ~3% improvement, 1204KB = +10%, 2048KB = +25%.
Improvements ~double with FFT lengths <= 1/2 L2 cache size.
PIII (non-Xeon): +6-8%; +12-15% for 96K FFT length. Speed increase appears
to be from increased L1 cache, which makes sense as accessing the L1 is 2-6x
faster than accessing L2.
Regards,
Ethan
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