> Accccckkkkkk! That was rather inexact wording. Let me try again...my > Celeron 400 based systems crunch exponents in the 384K FFT range at about > the same speed as George's PII-400 machine. However, at the 448K FFT size, > George's machine appears to be 20% or more faster than my Celeron 400s. > Could the 128K L2 cache of the Celeron chips (vs. the 512K L2 cache of the > PIIs) be the culprit? I think so. Yves Gallot mentioned something similar on the Primes-L list a while ago. This brings us to an interesting point. Should the primenet server start default assigning celeron's <384K FFT mersennes, and save the larger ones for PII's/PIII's? -Lucas _________________________________________________________________ Unsubscribe & list info -- http://www.scruz.net/~luke/signup.htm Mersenne Prime FAQ -- http://www.tasam.com/~lrwiman/FAQ-mers
