On Fri, 1 Dec 2000, Brian J. Beesley wrote:
> On 1 Dec 00, at 0:13, [EMAIL PROTECTED] wrote:
>
> [... snip ...]
> > How is any of this relevant to Mersenne testing? Well, fast 64-bit integer
> > ops should make a well-designed all-integer convolution algorithm
> > competitive with a floating-point-FFT-based one. However, neither of these
> > two is truly satisfying since each basically uses just half the
> > functionality (integer or floating-point) of the processor.
>
> Half the execution units ... but maybe there may already be a
> bottleneck e.g. in the memory bus throughput, or in the instruction
> decoder.
This is definitely an issue with the Alpha 21264, which can execute
6 instructions per clock (four integer, 2 floating) but can only
decode 4 instructions per clock.
> If we were free to design a processor optimized for mega-precision
> arithmetic, we'd have registers _much_ longer than 64 bits. We would
> probably also have multi-operand instructions, allowing e.g. elements
> of a radix-N FFT to be computed in a single instruction. At any rate
> we _definitely_ want to be able to evaultate a * b + c as fast as
> possible - and it is possible to calculate the result in the time
> taken to do just the multiplication.
> But we'd still need to move the operands between CPU registers and
> main memory. This is likely to continue to represent a bottleneck,
> which could only be got around by using very wide data busses and/or
> very fast (static) RAM - strategies which would result in expensive
> hardware systems.
Or a huge pipeline with banked memory. This would actually not be
extremely difficult: built a vector NTT butterfly ASIC with its
own DMA engines, and connect it to multibank DRAM arrays. What you'd
get is a vector processor which could execute convolution primitives.
Sometimes I wish I knew more about hardware...
jasonp
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