On 7 May 2001, at 2:04, Sandy Harris wrote:
> Might it just be the effect of slower cache? As I recall, the numbers were:
>
> P Pro 256 or 512K one CPU clock to deliver data
> P II 512 K two
> Celeron 128 K one
>
> and on some tasks, Celeron outperforms P II at the same clock because of
> this.
Though when I investigated why a C266 system I had outperformed a PII-
266 running Prime95, I found that the reason was that the LX chipset
on the PII was assuming that the memory was very slow, whereas the EX
chipset on the C266 system was taking advantage of the memory timing
information set in the PROM on the SDRAM boardlet.
>
> If the process is cache-bound and key data fits in both caches, this gives
> about the right numbers. P II cache runs at 333/2 which is to 200 roughly
> as .448 is to .515.
Key data does NOT fit in the caches. In fact if you look at the
timings page you will see that where the same processor is available
in "slow" 512K L2 cache & "fast" 256K L2 cache formats (e.g. PIII vs
PIIIE, or Slot A Athlon vs Socket A Athlon) the "slow" 512K cache
version usually runs Prime95 a few percent faster. The key is the
memory bus loading and the efficiency of access to the memory.
>
> Alternately. do you just need a differently optimised version of the code
> to get the best out of your P IIs?
No, the PPro and the PII are the same hardware architecture.
Regards
Brian Beesley
1775*2^332181+1 is prime! (100000 digits) Discovered 22-Apr-2001
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