Module: Mesa Branch: master Commit: 431b0ef9ee02fd5e52c989074650a078f96fea44 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=431b0ef9ee02fd5e52c989074650a078f96fea44
Author: Eric Anholt <[email protected]> Date: Wed Mar 17 09:43:58 2021 -0700 freedreno/a6xx: Rename the RB_BLIT_INFO.INTEGER field to SAMPLE_0. As @samuelig found, this is the field for disabling sample averaging and using sample 0 instead. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9661> --- src/freedreno/registers/adreno/a6xx.xml | 2 +- src/freedreno/vulkan/tu_clear_blit.c | 3 +-- src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 4 ++-- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml index f43da371ed9..8dffc4427e7 100644 --- a/src/freedreno/registers/adreno/a6xx.xml +++ b/src/freedreno/registers/adreno/a6xx.xml @@ -2126,7 +2126,7 @@ to upconvert to 32b float internally? <reg32 offset="0x88e3" name="RB_BLIT_INFO"> <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color restore? --> <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? --> - <bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably --> + <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging --> <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? --> <doc> For clearing depth/stencil diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c index aabd25c72a3..425f723969e 100644 --- a/src/freedreno/vulkan/tu_clear_blit.c +++ b/src/freedreno/vulkan/tu_clear_blit.c @@ -2383,8 +2383,7 @@ tu_emit_blit(struct tu_cmd_buffer *cmd, tu_cs_emit_regs(cs, A6XX_RB_BLIT_INFO( .unk0 = !resolve, .gmem = !resolve, - /* "integer" bit disables msaa resolve averaging */ - .integer = vk_format_is_int(attachment->format) | + .sample_0 = vk_format_is_int(attachment->format) | vk_format_is_depth_or_stencil(attachment->format))); tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 4); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index 7fdc0ebc6a0..0019a55c5e2 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -942,7 +942,7 @@ emit_restore_blit(struct fd_batch *batch, OUT_REG(ring, A6XX_RB_BLIT_INFO( .gmem = true, .unk0 = true, .depth = (buffer == FD_BUFFER_DEPTH), - .integer = util_format_is_pure_integer(psurf->format))); + .sample_0 = util_format_is_pure_integer(psurf->format))); emit_blit(batch, ring, base, psurf, stencil); } @@ -1256,7 +1256,7 @@ emit_resolve_blit(struct fd_batch *batch, } if (util_format_is_pure_integer(psurf->format)) - info |= A6XX_RB_BLIT_INFO_INTEGER; + info |= A6XX_RB_BLIT_INFO_SAMPLE_0; OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1); OUT_RING(ring, info); _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
