Module: Mesa Branch: asm-shader-rework-3 Commit: 71caa501e073eccdc59cb5dac630efa2b5e9d8be URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=71caa501e073eccdc59cb5dac630efa2b5e9d8be
Author: Ian Romanick <[email protected]> Date: Thu Oct 1 16:11:00 2009 -0700 NV vp3 parser: Support PUSHA and POPA instructions The grammar used here deviates from the grammar published in the spec, but it matches the behavior of Nvidia's assembler. --- src/mesa/shader/program_lexer.l | 2 ++ src/mesa/shader/program_parse.y | 17 ++++++++++++++++- 2 files changed, 18 insertions(+), 1 deletions(-) diff --git a/src/mesa/shader/program_lexer.l b/src/mesa/shader/program_lexer.l index a271bde..4fd8146 100644 --- a/src/mesa/shader/program_lexer.l +++ b/src/mesa/shader/program_lexer.l @@ -213,6 +213,8 @@ PK2H { return_opcode(require_NV_fp, VECTOR_OP, PK2H, 4); } PK2US { return_opcode(require_NV_fp, VECTOR_OP, PK2US, 5); } PK4B { return_opcode(require_NV_fp, VECTOR_OP, PK4B, 4); } PK4UB { return_opcode(require_NV_fp, VECTOR_OP, PK4UB, 5); } +PUSHA { return_opcode(require_NV_vp3, PUSHA_OP, PUSHA, 5); } +POPA { return_opcode(require_NV_vp3, POPA_OP, POPA, 4); } POW{szf}{cc}{sat} { return_opcode( 1, BINSC_OP, POW, 3); } RET { return_opcode(require_NV_vp2, FLOW_OP, RET, 3); } diff --git a/src/mesa/shader/program_parse.y b/src/mesa/shader/program_parse.y index 45254f6..878edef 100644 --- a/src/mesa/shader/program_parse.y +++ b/src/mesa/shader/program_parse.y @@ -151,7 +151,7 @@ static struct asm_instruction *asm_instruction_copy_ctor( /* Tokens for instructions */ %token <temp_inst> BIN_OP BINSC_OP SAMPLE_OP SCALAR_OP TRI_OP VECTOR_OP -%token <temp_inst> ARL_OP ARA_OP KIL SWZ TXD_OP BRA_OP FLOW_OP +%token <temp_inst> ARL_OP ARA_OP KIL SWZ TXD_OP BRA_OP FLOW_OP PUSHA_OP POPA_OP %token <integer> INTEGER %token <real> REAL @@ -189,6 +189,7 @@ static struct asm_instruction *asm_instruction_copy_ctor( %type <inst> SCALARop_instruction BINSCop_instruction BINop_instruction %type <inst> TRIop_instruction TXD_instruction SWZ_instruction SAMPLE_instruction %type <inst> KIL_instruction ARA_instruction BRA_instruction FLOWCC_instruction +%type <inst> ASTACK_instruction %type <dst_reg> dstReg maskedDstReg instResultAddr %type <src_reg> srcReg scalarUse scalarSrcReg swizzleSrcReg @@ -353,6 +354,7 @@ instruction: ALU_instruction ALU_instruction: ARA_instruction | ARL_instruction + | ASTACK_instruction | VECTORop_instruction | SCALARop_instruction | BINSCop_instruction @@ -382,6 +384,17 @@ ARA_instruction: ARA_OP instResultAddr ',' instOperandAddrVNS } ; +ASTACK_instruction: PUSHA_OP instOperandAddrVNS + { + $$ = asm_instruction_copy_ctor(& $1, NULL, & $2, NULL, NULL); + } + | POPA_OP instResultAddr + { + $$ = asm_instruction_copy_ctor(& $1, & $2, NULL, NULL, NULL); + } + ; + + VECTORop_instruction: VECTOR_OP maskedDstReg ',' swizzleSrcReg { $$ = asm_instruction_copy_ctor(& $1, & $2, & $4, NULL, NULL); @@ -2333,6 +2346,7 @@ asm_instruction_set_operands(struct asm_instruction *inst, * BRA (GL_NV_vertex_program2_option) * CAL (GL_NV_vertex_program2_option) * RET (GL_NV_vertex_program2_option) + * PUSHA (GL_NV_vertex_program3) */ if (dst == NULL) { init_dst_reg(& inst->Base.DstReg); @@ -2347,6 +2361,7 @@ asm_instruction_set_operands(struct asm_instruction *inst, * BRA (GL_NV_vertex_program2_option) * CAL (GL_NV_vertex_program2_option) * RET (GL_NV_vertex_program2_option) + * POPA (GL_NV_vertex_program3) */ if (src0 != NULL) { inst->Base.SrcReg[0] = src0->Base; _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
