Module: Mesa
Branch: asm-shader-rework-3
Commit: 192267c2be0dffe7838e11abaa58b1b7926c66c7
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=192267c2be0dffe7838e11abaa58b1b7926c66c7

Author: Ian Romanick <[email protected]>
Date:   Thu Oct  1 23:42:25 2009 -0700

ARB prog parser: Fix some incorrect address register mask handling

---

 src/mesa/shader/program_lexer.l |    2 +-
 src/mesa/shader/program_parse.y |   23 ++++++++++++++++++++++-
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/src/mesa/shader/program_lexer.l b/src/mesa/shader/program_lexer.l
index 4fd8146..60730ca 100644
--- a/src/mesa/shader/program_lexer.l
+++ b/src/mesa/shader/program_lexer.l
@@ -174,7 +174,7 @@ TEMP                      { yylval->integer = at_temp; 
return TEMP; }
 ABS{sz}{cc}{sat}   { return_opcode(             1, VECTOR_OP, ABS, 3); }
 ADD{sz}{cc}{sat}   { return_opcode(             1, BIN_OP, ADD, 3); }
 ARA                { return_opcode(require_NV_vp2, ARA_OP, ARA, 3); }
-ARL                { return_opcode(require_ARB_vp, ARL_OP, ARL, 3); }
+ARL                { return_opcode(require_ARB_vp, (require_NV_vp2) ? 
ARL_NV_OP : ARL_OP, ARL, 3); }
 ARR                { return_opcode(require_NV_vp2, ARL_OP, ARR, 3); }
 
 BRA                { return_opcode(require_NV_vp2, BRA_OP, BRA, 3); }
diff --git a/src/mesa/shader/program_parse.y b/src/mesa/shader/program_parse.y
index 878edef..76d5c43 100644
--- a/src/mesa/shader/program_parse.y
+++ b/src/mesa/shader/program_parse.y
@@ -105,6 +105,11 @@ static struct asm_instruction *asm_instruction_copy_ctor(
    } while(YYID(0))
 
 #define YYLEX_PARAM state->scanner
+
+#define SWIZZLE_XXXX MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)
+#define SWIZZLE_YYYY MAKE_SWIZZLE4(SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y)
+#define SWIZZLE_ZZZZ MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z)
+#define SWIZZLE_WWWW MAKE_SWIZZLE4(SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W)
 %}
 
 %pure-parser
@@ -151,7 +156,8 @@ static struct asm_instruction *asm_instruction_copy_ctor(
 
  /* Tokens for instructions */
 %token <temp_inst> BIN_OP BINSC_OP SAMPLE_OP SCALAR_OP TRI_OP VECTOR_OP
-%token <temp_inst> ARL_OP ARA_OP KIL SWZ TXD_OP BRA_OP FLOW_OP PUSHA_OP POPA_OP
+%token <temp_inst> KIL SWZ TXD_OP BRA_OP FLOW_OP
+%token <temp_inst> ARL_OP ARL_NV_OP ARA_OP PUSHA_OP POPA_OP
 
 %token <integer> INTEGER
 %token <real> REAL
@@ -372,10 +378,20 @@ FlowInstruction: BRA_instruction
        | FLOWCC_instruction
        ;
 
+       /* ARL_OP is returned by the lexer for the input "ARL" in
+        * GL_ARB_vertex_program mode.  In GL_NV_vertex_program2_option mode
+        * the lexer returns ARL_NV_OP for the same string.  This allows the
+        * parser to differentiate between the different source opperand types
+        * for the two flavors of the instruction.
+        */
 ARL_instruction: ARL_OP instResultAddr ',' scalarSrcReg
        {
           $$ = asm_instruction_copy_ctor(& $1, & $2, & $4, NULL, NULL);
        }
+       | ARL_NV_OP instResultAddr ',' swizzleSrcReg
+       {
+          $$ = asm_instruction_copy_ctor(& $1, & $2, & $4, NULL, NULL);
+       }
        ;
 
 ARA_instruction: ARA_OP instResultAddr ',' instOperandAddrVNS
@@ -390,6 +406,11 @@ ASTACK_instruction: PUSHA_OP instOperandAddrVNS
        }
        | POPA_OP instResultAddr
        {
+          if ($2.WriteMask != WRITEMASK_XYZW) {
+             yyerror(& @2, state, "POPA only supports .xyzw write mask");
+             YYERROR;
+          }
+
           $$ = asm_instruction_copy_ctor(& $1, & $2, NULL, NULL, NULL);
        }
        ;

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