Module: Mesa Branch: main Commit: ee9f0e78c175416b5523cb086517bf7304109aa7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee9f0e78c175416b5523cb086517bf7304109aa7
Author: Danylo Piliaiev <[email protected]> Date: Thu Aug 19 14:53:23 2021 +0300 ir3: prohibit folding of half->full conversion into mul.s24/u24 mul.s24/u24 always return 32b result regardless of its sources size, hence we cannot guarantee the high 16b of dst being zero or sign extended. Fixes cts tests on a650: dEQP-VK.spirv_assembly.type.scalar.i16.mul_test_high_part_zero_* Signed-off-by: Danylo Piliaiev <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12471> --- src/freedreno/ir3/ir3_cf.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/freedreno/ir3/ir3_cf.c b/src/freedreno/ir3/ir3_cf.c index dc05738985f..4f8d85f429c 100644 --- a/src/freedreno/ir3/ir3_cf.c +++ b/src/freedreno/ir3/ir3_cf.c @@ -38,6 +38,13 @@ is_safe_conv(struct ir3_instruction *instr, type_t src_type, opc_t *src_opc) full_type(instr->cat1.src_type) != full_type(instr->cat1.dst_type)) return false; + /* mul.s24/u24 always return 32b result regardless of its sources size, + * hence we cannot guarantee the high 16b of dst being zero or sign extended. + */ + if ((*src_opc == OPC_MUL_S24 || *src_opc == OPC_MUL_U24) && + type_size(instr->cat1.src_type) == 16) + return false; + struct ir3_register *dst = instr->dsts[0]; struct ir3_register *src = instr->srcs[0];
