Module: Mesa Branch: main Commit: 6fc38d3b077388c9868785558a959e853a176258 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6fc38d3b077388c9868785558a959e853a176258
Author: Marek Olšák <[email protected]> Date: Tue Aug 17 12:57:03 2021 -0400 radeonsi: allow arbitrary swizzle modes for displayable DCC by adding retile shader variants Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12430> --- src/gallium/drivers/radeonsi/si_compute_blit.c | 14 +++++--------- src/gallium/drivers/radeonsi/si_pipe.c | 6 ++++-- src/gallium/drivers/radeonsi/si_pipe.h | 2 +- 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index 66b3ed5036c..fa0392e0214 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -613,16 +613,12 @@ void si_retile_dcc(struct si_context *sctx, struct si_texture *tex) sctx->cs_user_data[2] = (tex->surface.u.gfx9.color.display_dcc_pitch_max + 1) | (tex->surface.u.gfx9.color.display_dcc_height << 16); - /* There is only 1 shader variant because ac_surface only supports displayable DCC - * with one swizzle mode and 32bpp. - */ + /* We have only 1 variant per bpp for now, so expect 32 bpp. */ assert(tex->surface.bpe == 4); - assert(sctx->chip_class != GFX9 || tex->surface.u.gfx9.swizzle_mode == 25); /* 64KB_S_X */ - assert(sctx->chip_class != GFX10 || tex->surface.u.gfx9.swizzle_mode == 27); /* 64KB_R_X */ - assert(sctx->chip_class != GFX10_3 || tex->surface.u.gfx9.swizzle_mode == 27); /* 64KB_R_X */ - if (!sctx->cs_dcc_retile) - sctx->cs_dcc_retile = si_create_dcc_retile_cs(sctx, &tex->surface); + void **shader = &sctx->cs_dcc_retile[tex->surface.u.gfx9.swizzle_mode]; + if (!*shader) + *shader = si_create_dcc_retile_cs(sctx, &tex->surface); /* Dispatch compute. */ unsigned width = DIV_ROUND_UP(tex->buffer.b.b.width0, tex->surface.u.gfx9.color.dcc_block_width); @@ -638,7 +634,7 @@ void si_retile_dcc(struct si_context *sctx, struct si_texture *tex) info.grid[1] = DIV_ROUND_UP(height, info.block[1]); info.grid[2] = 1; - si_launch_grid_internal_ssbos(sctx, &info, sctx->cs_dcc_retile, SI_OP_SYNC_BEFORE, + si_launch_grid_internal_ssbos(sctx, &info, *shader, SI_OP_SYNC_BEFORE, SI_COHERENCY_CB_META, 1, &sb, 0x1); /* Don't flush caches. L2 will be flushed by the kernel fence. */ diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 0ca0ce8209e..ce0755413cf 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -251,8 +251,10 @@ static void si_destroy_context(struct pipe_context *context) sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_12bytes_buffer); if (sctx->cs_dcc_decompress) sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_decompress); - if (sctx->cs_dcc_retile) - sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile); + for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_dcc_retile); i++) { + if (sctx->cs_dcc_retile[i]) + sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile[i]); + } if (sctx->no_velems_state) sctx->b.delete_vertex_elements_state(&sctx->b, sctx->no_velems_state); diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index a8722b20fa3..17f42bd7ee8 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -958,7 +958,7 @@ struct si_context { void *cs_clear_render_target_1d_array; void *cs_clear_12bytes_buffer; void *cs_dcc_decompress; - void *cs_dcc_retile; + void *cs_dcc_retile[32]; void *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */ struct si_screen *screen; struct pipe_debug_callback debug;
