Module: Mesa Branch: main Commit: eb06e6e6cd61879d929fc390571a3dd67e41fdf0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb06e6e6cd61879d929fc390571a3dd67e41fdf0
Author: Joshua Ashton <[email protected]> Date: Mon Sep 27 22:41:23 2021 +0100 radv: Add noatocdithering option to RADV_DEBUG Was useful in testing a difference between D3D and VK ATOC rendering earlier today, would be nice to check this more easily in future. Signed-off-by: Joshua Ashton <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13069> --- docs/envvars.rst | 2 ++ src/amd/vulkan/radv_debug.h | 1 + src/amd/vulkan/radv_device.c | 1 + src/amd/vulkan/radv_pipeline.c | 15 ++++++++++++--- 4 files changed, 16 insertions(+), 3 deletions(-) diff --git a/docs/envvars.rst b/docs/envvars.rst index 16a83d21cfd..04b4e636e71 100644 --- a/docs/envvars.rst +++ b/docs/envvars.rst @@ -581,6 +581,8 @@ RADV driver environment variables class of application bugs appearing as flickering. ``metashaders`` dump internal meta shaders + ``noatocdithering`` + disable dithering for alpha to coverage ``nobinning`` disable primitive binning ``nocache`` diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h index 5a0f2958600..df50965ccb7 100644 --- a/src/amd/vulkan/radv_debug.h +++ b/src/amd/vulkan/radv_debug.h @@ -62,6 +62,7 @@ enum { RADV_DEBUG_NO_DISPLAY_DCC = 1ull << 31, RADV_DEBUG_NO_TC_COMPAT_CMASK = 1ull << 32, RADV_DEBUG_NO_VRS_FLAT_SHADING = 1ull << 33, + RADV_DEBUG_NO_ATOC_DITHERING = 1ull << 34, }; enum { diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index aee372a6672..f62379ba762 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -823,6 +823,7 @@ static const struct debug_control radv_debug_options[] = { {"nodisplaydcc", RADV_DEBUG_NO_DISPLAY_DCC}, {"notccompatcmask", RADV_DEBUG_NO_TC_COMPAT_CMASK}, {"novrsflatshading", RADV_DEBUG_NO_VRS_FLAT_SHADING}, + {"noatocdithering", RADV_DEBUG_NO_ATOC_DITHERING}, {NULL, 0}}; const char * diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 9e2f610c62c..29e23bb465a 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -639,9 +639,18 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline, cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY); } - blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) | - S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) | - S_028B70_OFFSET_ROUND(1); + if (pipeline->device->instance->debug_flags & RADV_DEBUG_NO_ATOC_DITHERING) + { + blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) | + S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) | + S_028B70_OFFSET_ROUND(0); + } + else + { + blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) | + S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) | + S_028B70_OFFSET_ROUND(1); + } if (vkms && vkms->alphaToCoverageEnable) { blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
