Module: Mesa Branch: main Commit: 4cb008719c0fc9705dd16416e99ff7ae1b3a7fa1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4cb008719c0fc9705dd16416e99ff7ae1b3a7fa1
Author: Marek Olšák <[email protected]> Date: Sat Sep 25 04:53:47 2021 -0400 radeonsi: fix a depth texturing performance regression on gfx6-7 Fixes: 0580d4c1 "radeonsi: enable HTILE with mipmapping on gfx9+" Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5398 Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13048> --- src/gallium/drivers/radeonsi/si_pipe.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 60a58957375..d0bc9c4de87 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1765,7 +1765,19 @@ static inline bool si_htile_enabled(struct si_texture *tex, unsigned level, unsi if (zs_mask == PIPE_MASK_S && (tex->htile_stencil_disabled || !tex->surface.has_stencil)) return false; - return tex->is_depth && tex->surface.meta_offset && level < tex->surface.num_meta_levels; + if (!tex->is_depth || !tex->surface.meta_offset) + return false; + + struct si_screen *sscreen = (struct si_screen *)tex->buffer.b.b.screen; + if (sscreen->info.chip_class >= GFX8) { + return level < tex->surface.num_meta_levels; + } else { + /* GFX6-7 don't have TC-compatible HTILE, which means they have to run + * a decompression pass for every mipmap level before texturing, so compress + * only one level to reduce the number of decompression passes to a minimum. + */ + return level == 0; + } } static inline bool vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level,
