Module: Mesa Branch: main Commit: e0efc1eafee8b12bf2e89da025cb7683dcce58ec URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0efc1eafee8b12bf2e89da025cb7683dcce58ec
Author: Samuel Pitoiset <[email protected]> Date: Mon Sep 27 15:17:59 2021 +0200 radv: remove radv_shader_variant_key completely Die radv_shader_variant_key, die! Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timur Kristóf <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13085> --- src/amd/vulkan/radv_pipeline.c | 59 +++++------------------------------- src/amd/vulkan/radv_private.h | 2 -- src/amd/vulkan/radv_shader.c | 1 - src/amd/vulkan/radv_shader.h | 64 --------------------------------------- src/amd/vulkan/radv_shader_info.c | 2 +- 5 files changed, 9 insertions(+), 119 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 1d44caa3da4..2de761e6d89 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2740,39 +2740,6 @@ radv_nir_stage_uses_xfb(const nir_shader *nir) return uses_xfb; } -static void -radv_fill_shader_keys(struct radv_device *device, struct radv_shader_variant_key *keys, - const struct radv_pipeline_key *key, nir_shader **nir) -{ - keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->vs.instance_rate_inputs; - keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vs.vertex_post_shuffle; - for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) { - keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->vs.instance_rate_divisors[i]; - keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vs.vertex_attribute_formats[i]; - keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vs.vertex_attribute_bindings[i]; - keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vs.vertex_attribute_offsets[i]; - keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vs.vertex_attribute_strides[i]; - keys[MESA_SHADER_VERTEX].vs.alpha_adjust[i] = key->vs.vertex_alpha_adjust[i]; - } - for (unsigned i = 0; i < MAX_VBS; ++i) - keys[MESA_SHADER_VERTEX].vs.vertex_binding_align[i] = key->vs.vertex_binding_align[i]; - keys[MESA_SHADER_VERTEX].vs.provoking_vtx_last = key->vs.provoking_vtx_last; - keys[MESA_SHADER_VERTEX].vs.topology = key->vs.topology; - - if (nir[MESA_SHADER_TESS_CTRL]) { - keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tcs.tess_input_vertices; - } - - for (int i = 0; i < MESA_SHADER_STAGES; ++i) - keys[i].has_multiview_view_index = key->has_multiview_view_index; - - keys[MESA_SHADER_FRAGMENT].fs.col_format = key->ps.col_format; - keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->ps.is_int8; - keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->ps.is_int10; - keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->ps.log2_ps_iter_samples; - keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->ps.num_samples; -} - static uint8_t radv_get_wave_size(struct radv_device *device, const VkPipelineShaderStageCreateInfo *pStage, gl_shader_stage stage, const struct radv_shader_info *info) @@ -2800,8 +2767,7 @@ static void radv_fill_shader_info(struct radv_pipeline *pipeline, const VkPipelineShaderStageCreateInfo **pStages, const struct radv_pipeline_key *pipeline_key, - struct radv_shader_variant_key *keys, struct radv_shader_info *infos, - nir_shader **nir) + struct radv_shader_info *infos, nir_shader **nir) { struct radv_device *device = pipeline->device; unsigned active_stages = 0; @@ -2875,8 +2841,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, if (nir[MESA_SHADER_FRAGMENT]) { radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]); radv_nir_shader_info_pass(pipeline->device, nir[MESA_SHADER_FRAGMENT], pipeline->layout, - pipeline_key, &keys[MESA_SHADER_FRAGMENT], - &infos[MESA_SHADER_FRAGMENT]); + pipeline_key, &infos[MESA_SHADER_FRAGMENT]); assert(pipeline->graphics.last_vgt_api_stage != MESA_SHADER_NONE); if (infos[MESA_SHADER_FRAGMENT].ps.prim_id_input) { @@ -2913,8 +2878,6 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 && nir[MESA_SHADER_TESS_CTRL]) { struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]}; - struct radv_shader_variant_key *key = &keys[MESA_SHADER_TESS_CTRL]; - key->tcs.vs_key = keys[MESA_SHADER_VERTEX].vs; radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]); @@ -2923,7 +2886,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, for (int i = 0; i < 2; i++) { radv_nir_shader_info_pass(pipeline->device, combined_nir[i], pipeline->layout, pipeline_key, - key, &infos[MESA_SHADER_TESS_CTRL]); + &infos[MESA_SHADER_TESS_CTRL]); } filled_stages |= (1 << MESA_SHADER_VERTEX); @@ -2949,7 +2912,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, for (int i = 0; i < 2; i++) { radv_nir_shader_info_pass(pipeline->device, combined_nir[i], pipeline->layout, pipeline_key, - &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY]); + &infos[MESA_SHADER_GEOMETRY]); } filled_stages |= (1 << pre_stage); @@ -2960,8 +2923,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, while (active_stages) { int i = u_bit_scan(&active_stages); radv_nir_shader_info_init(&infos[i]); - radv_nir_shader_info_pass(pipeline->device, nir[i], pipeline->layout, pipeline_key, &keys[i], - &infos[i]); + radv_nir_shader_info_pass(pipeline->device, nir[i], pipeline->layout, pipeline_key, &infos[i]); } if (nir[MESA_SHADER_COMPUTE]) { @@ -3353,7 +3315,6 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device, }; nir_shader *nir[MESA_SHADER_STAGES] = {0}; struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL}; - struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}}; struct radv_shader_info infos[MESA_SHADER_STAGES] = {0}; unsigned char hash[20], gs_copy_hash[20]; bool keep_executable_info = @@ -3467,8 +3428,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device, gather_tess_info(device, nir, infos, pipeline_key); } - radv_fill_shader_keys(device, keys, pipeline_key, nir); - radv_fill_shader_info(pipeline, pStages, pipeline_key, keys, infos, nir); + radv_fill_shader_info(pipeline, pStages, pipeline_key, infos, nir); bool pipeline_has_ngg = (nir[MESA_SHADER_VERTEX] && infos[MESA_SHADER_VERTEX].is_ngg) || (nir[MESA_SHADER_TESS_EVAL] && infos[MESA_SHADER_TESS_EVAL].is_ngg); @@ -3561,7 +3521,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device, if (lowered_ngg) { uint64_t ps_inputs_read = nir[MESA_SHADER_FRAGMENT] ? nir[MESA_SHADER_FRAGMENT]->info.inputs_read : 0; bool consider_culling = radv_consider_culling(device, nir[i], ps_inputs_read); - radv_lower_ngg(device, nir[i], &infos[i], pipeline_key, &keys[i], consider_culling); + radv_lower_ngg(device, nir[i], &infos[i], pipeline_key, consider_culling); } radv_optimize_nir_algebraic(nir[i], io_to_mem || lowered_ngg || i == MESA_SHADER_COMPUTE); @@ -3604,10 +3564,9 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device, struct radv_shader_binary *gs_copy_binary = NULL; if (!pipeline_has_ngg) { struct radv_shader_info info = {0}; - struct radv_shader_variant_key key = {0}; radv_nir_shader_info_pass(device, nir[MESA_SHADER_GEOMETRY], pipeline->layout, pipeline_key, - &key, &info); + &info); info.wave_size = 64; /* Wave32 not supported. */ info.workgroup_size = 64; /* HW VS: separate waves, no workgroups */ info.ballot_bit_size = 64; @@ -3649,8 +3608,6 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device, if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) { if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) { struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]}; - struct radv_shader_variant_key *key = &keys[MESA_SHADER_TESS_CTRL]; - key->tcs.vs_key = keys[MESA_SHADER_VERTEX].vs; radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 622c818c934..59376b998bf 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2585,12 +2585,10 @@ void llvm_compile_shader(struct radv_device *device, unsigned shader_count, /* radv_shader_info.h */ struct radv_shader_info; -struct radv_shader_variant_key; void radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir, const struct radv_pipeline_layout *layout, const struct radv_pipeline_key *pipeline_key, - const struct radv_shader_variant_key *key, struct radv_shader_info *info); void radv_nir_shader_info_init(struct radv_shader_info *info); diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 5921572ca70..b693e37525d 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -921,7 +921,6 @@ radv_consider_culling(struct radv_device *device, struct nir_shader *nir, void radv_lower_ngg(struct radv_device *device, struct nir_shader *nir, struct radv_shader_info *info, const struct radv_pipeline_key *pl_key, - struct radv_shader_variant_key *key, bool consider_culling) { /* TODO: support the LLVM backend with the NIR lowering */ diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index d6159dfebc6..b2106351294 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -47,69 +47,6 @@ struct radv_pipeline; struct radv_pipeline_cache; struct radv_pipeline_key; -struct radv_vs_out_key { - uint32_t as_es : 1; - uint32_t as_ls : 1; - uint32_t as_ngg : 1; - uint32_t as_ngg_passthrough : 1; - uint32_t export_clip_dists : 1; -}; - -struct radv_vs_variant_key { - struct radv_vs_out_key out; - - uint32_t instance_rate_inputs; - uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS]; - uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS]; - uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS]; - uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS]; - uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS]; - uint8_t vertex_binding_align[MAX_VBS]; - - /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW. - * so we may need to fix it up. */ - enum ac_fetch_format alpha_adjust[MAX_VERTEX_ATTRIBS]; - - /* For some formats the channels have to be shuffled. */ - uint32_t post_shuffle; - - /* Topology. */ - uint8_t topology; - - /* Provoking vertex mode. */ - bool provoking_vtx_last; -}; - -struct radv_tes_variant_key { - struct radv_vs_out_key out; -}; - -struct radv_tcs_variant_key { - struct radv_vs_variant_key vs_key; - unsigned input_vertices; -}; - -struct radv_fs_variant_key { - uint32_t col_format; - uint8_t log2_ps_iter_samples; - uint8_t num_samples; - uint32_t is_int8; - uint32_t is_int10; -}; - -struct radv_shader_variant_key { - union { - struct radv_vs_variant_key vs; - struct radv_fs_variant_key fs; - struct radv_tes_variant_key tes; - struct radv_tcs_variant_key tcs; - - /* A common prefix of the vs and tes keys. */ - struct radv_vs_out_key vs_common_out; - }; - bool has_multiview_view_index; -}; - struct radv_pipeline_key { uint32_t has_multiview_view_index : 1; uint32_t optimisations_disabled : 1; @@ -597,7 +534,6 @@ bool radv_lower_io_to_mem(struct radv_device *device, struct nir_shader *nir, void radv_lower_ngg(struct radv_device *device, struct nir_shader *nir, struct radv_shader_info *info, const struct radv_pipeline_key *pl_key, - struct radv_shader_variant_key *key, bool consider_culling); bool radv_consider_culling(struct radv_device *device, struct nir_shader *nir, diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index b722bdddab3..ec3822c3b8a 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -556,7 +556,7 @@ void radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir, const struct radv_pipeline_layout *layout, const struct radv_pipeline_key *pipeline_key, - const struct radv_shader_variant_key *key, struct radv_shader_info *info) + struct radv_shader_info *info) { struct nir_function *func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
