Module: Mesa Branch: main Commit: 1eb428fa9fd2d6b03a9bc405e69725fde4030fa6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1eb428fa9fd2d6b03a9bc405e69725fde4030fa6
Author: Samuel Pitoiset <[email protected]> Date: Mon Sep 27 13:23:48 2021 +0200 radv: pass the pipeline key to the shader info pass Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timur Kristóf <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13085> --- src/amd/vulkan/radv_pipeline.c | 18 +++++++++--------- src/amd/vulkan/radv_private.h | 1 + src/amd/vulkan/radv_shader_info.c | 11 ++++++----- 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 539f1443b83..e689f9b432c 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2872,7 +2872,8 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, if (nir[MESA_SHADER_FRAGMENT]) { radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]); radv_nir_shader_info_pass(pipeline->device, nir[MESA_SHADER_FRAGMENT], pipeline->layout, - &keys[MESA_SHADER_FRAGMENT], &infos[MESA_SHADER_FRAGMENT]); + pipeline_key, &keys[MESA_SHADER_FRAGMENT], + &infos[MESA_SHADER_FRAGMENT]); assert(pipeline->graphics.last_vgt_api_stage != MESA_SHADER_NONE); if (infos[MESA_SHADER_FRAGMENT].ps.prim_id_input) { @@ -2915,8 +2916,8 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]); for (int i = 0; i < 2; i++) { - radv_nir_shader_info_pass(pipeline->device, combined_nir[i], pipeline->layout, key, - &infos[MESA_SHADER_TESS_CTRL]); + radv_nir_shader_info_pass(pipeline->device, combined_nir[i], pipeline->layout, pipeline_key, + key, &infos[MESA_SHADER_TESS_CTRL]); } filled_stages |= (1 << MESA_SHADER_VERTEX); @@ -2932,7 +2933,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]); for (int i = 0; i < 2; i++) { - radv_nir_shader_info_pass(pipeline->device, combined_nir[i], pipeline->layout, + radv_nir_shader_info_pass(pipeline->device, combined_nir[i], pipeline->layout, pipeline_key, &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY]); } @@ -2944,7 +2945,8 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, while (active_stages) { int i = u_bit_scan(&active_stages); radv_nir_shader_info_init(&infos[i]); - radv_nir_shader_info_pass(pipeline->device, nir[i], pipeline->layout, &keys[i], &infos[i]); + radv_nir_shader_info_pass(pipeline->device, nir[i], pipeline->layout, pipeline_key, &keys[i], + &infos[i]); } if (nir[MESA_SHADER_COMPUTE]) { @@ -3594,10 +3596,8 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device, struct radv_shader_info info = {0}; struct radv_shader_variant_key key = {0}; - key.has_multiview_view_index = keys[MESA_SHADER_GEOMETRY].has_multiview_view_index; - - radv_nir_shader_info_pass(device, nir[MESA_SHADER_GEOMETRY], pipeline->layout, &key, - &info); + radv_nir_shader_info_pass(device, nir[MESA_SHADER_GEOMETRY], pipeline->layout, pipeline_key, + &key, &info); info.wave_size = 64; /* Wave32 not supported. */ info.workgroup_size = 64; /* HW VS: separate waves, no workgroups */ info.ballot_bit_size = 64; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 27a87ec67b1..622c818c934 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2589,6 +2589,7 @@ struct radv_shader_variant_key; void radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir, const struct radv_pipeline_layout *layout, + const struct radv_pipeline_key *pipeline_key, const struct radv_shader_variant_key *key, struct radv_shader_info *info); diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index de1daa7266d..e1eb3491bcd 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -321,7 +321,7 @@ gather_info_block(const nir_shader *nir, const nir_block *block, struct radv_sha static void gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var, - struct radv_shader_info *info, const struct radv_shader_variant_key *key) + const struct radv_pipeline_key *key, struct radv_shader_info *info) { unsigned attrib_count = glsl_count_attribute_slots(var->type, true); @@ -409,11 +409,11 @@ gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var, static void gather_info_input_decl(const nir_shader *nir, const nir_variable *var, - struct radv_shader_info *info, const struct radv_shader_variant_key *key) + const struct radv_pipeline_key *key, struct radv_shader_info *info) { switch (nir->info.stage) { case MESA_SHADER_VERTEX: - gather_info_input_decl_vs(nir, var, info, key); + gather_info_input_decl_vs(nir, var, key, info); break; case MESA_SHADER_FRAGMENT: gather_info_input_decl_ps(nir, var, info); @@ -556,6 +556,7 @@ radv_nir_shader_info_init(struct radv_shader_info *info) void radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir, const struct radv_pipeline_layout *layout, + const struct radv_pipeline_key *pipeline_key, const struct radv_shader_variant_key *key, struct radv_shader_info *info) { struct nir_function *func = (struct nir_function *)exec_list_get_head_const(&nir->functions); @@ -574,7 +575,7 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n } nir_foreach_shader_in_variable (variable, nir) - gather_info_input_decl(nir, variable, info, key); + gather_info_input_decl(nir, variable, pipeline_key, info); nir_foreach_block (block, func->impl) { gather_info_block(nir, block, info); @@ -587,7 +588,7 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n gather_xfb_info(nir, info); /* Make sure to export the LayerID if the subpass has multiviews. */ - if (key->has_multiview_view_index) { + if (pipeline_key->has_multiview_view_index) { switch (nir->info.stage) { case MESA_SHADER_VERTEX: info->vs.outinfo.writes_layer = true;
