Module: Mesa Branch: main Commit: 591e3296cd24869581e75f664a53873b64b042ea URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=591e3296cd24869581e75f664a53873b64b042ea
Author: Samuel Pitoiset <[email protected]> Date: Thu Apr 14 09:20:14 2022 +0200 radv: clarify why STAGE_2_CLEAR_BIT needs to wait for CP DMA to be idle To clarify that other clear operations like vkCmdFillBuffer() are implicitly synchronized. So, STAGE_2_CLEAR_BIT is only needed for vkCmdUpdateBuffer() in some rare cases (GFX10+ dGPUs with GTT BOs). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15943> --- src/amd/vulkan/radv_cmd_buffer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 502e1792eff..7a8c98de3fd 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -8461,7 +8461,9 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfo *dep_inf } /* Make sure CP DMA is idle because the driver might have performed a DMA operation for copying a - * buffer (or a MSAA image using FMASK) or updated a buffer which is a transfer operation. + * buffer (or a MSAA image using FMASK). Note that updating a buffer is considered a clear + * operation but it might also use a CP DMA copy in some rare situations. Other operations using + * a CP DMA clear are implicitly synchronized (see CP_DMA_SYNC). */ if (src_stage_mask & (VK_PIPELINE_STAGE_2_COPY_BIT | VK_PIPELINE_STAGE_2_CLEAR_BIT |
