Module: Mesa Branch: main Commit: 51ea72e621e4aa93c1bb3f7e3c6c146e524bc2f4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=51ea72e621e4aa93c1bb3f7e3c6c146e524bc2f4
Author: Samuel Pitoiset <[email protected]> Date: Thu Apr 14 12:57:44 2022 +0200 radv: remove redundant VK_PIPELINE_STAGE_2_TRANSFER_BIT for CP DMA idle They are equivalent. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15943> --- src/amd/vulkan/radv_cmd_buffer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 7a8c98de3fd..1ea7045c511 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -8467,8 +8467,8 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfo *dep_inf */ if (src_stage_mask & (VK_PIPELINE_STAGE_2_COPY_BIT | VK_PIPELINE_STAGE_2_CLEAR_BIT | - VK_PIPELINE_STAGE_2_TRANSFER_BIT | VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT | - VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT)) + VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT | + VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT)) si_cp_dma_wait_for_idle(cmd_buffer); cmd_buffer->state.flush_bits |= dst_flush_bits;
