Module: Mesa Branch: main Commit: 2ae357aa23a39573ef0de33efa9a1ec2f4fbfd60 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ae357aa23a39573ef0de33efa9a1ec2f4fbfd60
Author: Qiang Yu <[email protected]> Date: Thu Jun 30 17:06:51 2022 +0800 nir: add nir_intrinsic_load_num_vertices_per_primitive_amd This is used in streamout as radeonsi pass this value for VS by arg. Reviewed-by: Timur Kristóf <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654> --- src/compiler/nir/nir_divergence_analysis.c | 1 + src/compiler/nir/nir_intrinsics.py | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index 0f6698eeca3..de5f9d74f48 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -183,6 +183,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_lshs_vertex_stride_amd: case nir_intrinsic_load_hs_out_patch_data_offset_amd: case nir_intrinsic_load_clip_half_line_width_amd: + case nir_intrinsic_load_num_vertices_per_primitive_amd: is_divergent = false; break; diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 0b830ccc466..e8eb5089322 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1424,6 +1424,9 @@ system_value("hs_out_patch_data_offset_amd", 1) # line_width * 0.5 / abs(viewport_scale[2]) system_value("clip_half_line_width_amd", 2) +# Number of vertices in a primitive +system_value("num_vertices_per_primitive_amd", 1) + # V3D-specific instrinc for tile buffer color reads. # # The hardware requires that we read the samples and components of a pixel
