Module: Mesa Branch: main Commit: 5c2d710064dd039836a82f6c2a7b76c494cc0c86 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c2d710064dd039836a82f6c2a7b76c494cc0c86
Author: Qiang Yu <[email protected]> Date: Thu Jun 30 17:37:03 2022 +0800 nir: add nir_intrinsic_load_streamout_buffer_amd Reviewed-by: Timur Kristóf <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654> --- src/compiler/nir/nir_divergence_analysis.c | 1 + src/compiler/nir/nir_intrinsics.py | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index de5f9d74f48..55f5df81e66 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -184,6 +184,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_hs_out_patch_data_offset_amd: case nir_intrinsic_load_clip_half_line_width_amd: case nir_intrinsic_load_num_vertices_per_primitive_amd: + case nir_intrinsic_load_streamout_buffer_amd: is_divergent = false; break; diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index e8eb5089322..39ae64fd1a9 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1427,6 +1427,10 @@ system_value("clip_half_line_width_amd", 2) # Number of vertices in a primitive system_value("num_vertices_per_primitive_amd", 1) +# Load streamout buffer desc +# BASE = buffer index +intrinsic("load_streamout_buffer_amd", dest_comp=4, indices=[BASE], bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) + # V3D-specific instrinc for tile buffer color reads. # # The hardware requires that we read the samples and components of a pixel
