Module: Mesa Branch: main Commit: 02129eee3aa7f6ad02cd9b0fa48b26b44d15575c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=02129eee3aa7f6ad02cd9b0fa48b26b44d15575c
Author: Kenneth Graunke <[email protected]> Date: Mon Jan 9 15:02:44 2023 -0800 intel/compiler: Eliminate SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT The only reason for the separate opcode was because of the overlapping BRW_AOP_* enums, making it impossible to tell whether a particular AOP was the integer or float operation. Now that we use the lsc_opcode enums, we can just have the legacy lowering inspect the opcode and select the right descriptor. No need for a separate opcode. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rohan Garg <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20604> --- src/intel/compiler/brw_eu.h | 16 ++++++++++++++++ src/intel/compiler/brw_eu_defines.h | 1 - src/intel/compiler/brw_fs.cpp | 2 -- src/intel/compiler/brw_fs_copy_propagation.cpp | 1 - src/intel/compiler/brw_fs_dead_code_eliminate.cpp | 1 - src/intel/compiler/brw_fs_nir.cpp | 8 ++++---- src/intel/compiler/brw_lower_logical_sends.cpp | 23 ++++++++++------------- src/intel/compiler/brw_shader.cpp | 3 --- 8 files changed, 30 insertions(+), 25 deletions(-) diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index a08b83a79dc..0841dc0fb46 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -1240,6 +1240,22 @@ lsc_opcode_is_atomic(enum lsc_opcode opcode) } } +static inline bool +lsc_opcode_is_atomic_float(enum lsc_opcode opcode) +{ + switch (opcode) { + case LSC_OP_ATOMIC_FADD: + case LSC_OP_ATOMIC_FSUB: + case LSC_OP_ATOMIC_FMIN: + case LSC_OP_ATOMIC_FMAX: + case LSC_OP_ATOMIC_FCMPXCHG: + return true; + + default: + return false; + } +} + static inline unsigned lsc_op_num_data_values(unsigned _op) { diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 97c6d6b66b8..15add869ce7 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -388,7 +388,6 @@ enum opcode { */ VEC4_OPCODE_UNTYPED_ATOMIC, SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, - SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL, VEC4_OPCODE_UNTYPED_SURFACE_READ, SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, VEC4_OPCODE_UNTYPED_SURFACE_WRITE, diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index e7bc721579c..844a54303ed 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -807,7 +807,6 @@ fs_inst::components_read(unsigned i) const return 1; case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: { assert(src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == IMM && src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM); @@ -5173,7 +5172,6 @@ get_lowered_simd_width(const struct brw_compiler *compiler, return 8; case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp b/src/intel/compiler/brw_fs_copy_propagation.cpp index 3f223c92d5c..b4b48684898 100644 --- a/src/intel/compiler/brw_fs_copy_propagation.cpp +++ b/src/intel/compiler/brw_fs_copy_propagation.cpp @@ -982,7 +982,6 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry) case SHADER_OPCODE_SAMPLEINFO_LOGICAL: case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: diff --git a/src/intel/compiler/brw_fs_dead_code_eliminate.cpp b/src/intel/compiler/brw_fs_dead_code_eliminate.cpp index ed7ab3ebdc9..5964acf47f4 100644 --- a/src/intel/compiler/brw_fs_dead_code_eliminate.cpp +++ b/src/intel/compiler/brw_fs_dead_code_eliminate.cpp @@ -57,7 +57,6 @@ can_omit_write(const fs_inst *inst) { switch (inst->opcode) { case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: return true; default: diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 1ed5fa977ba..cc2d3221cb2 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -6051,7 +6051,7 @@ fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder &bld, switch (nir_dest_bit_size(instr->dest)) { case 16: { fs_reg dest32 = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL, + bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, retype(dest32, dest.type), srcs, SURFACE_LOGICAL_NUM_SRCS); bld.MOV(retype(dest, BRW_REGISTER_TYPE_UW), @@ -6061,7 +6061,7 @@ fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder &bld, case 32: case 64: - bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL, + bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, dest, srcs, SURFACE_LOGICAL_NUM_SRCS); break; default: @@ -6179,7 +6179,7 @@ fs_visitor::nir_emit_shared_atomic_float(const fs_builder &bld, switch (nir_dest_bit_size(instr->dest)) { case 16: { fs_reg dest32 = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL, + bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, retype(dest32, dest.type), srcs, SURFACE_LOGICAL_NUM_SRCS); bld.MOV(retype(dest, BRW_REGISTER_TYPE_UW), @@ -6189,7 +6189,7 @@ fs_visitor::nir_emit_shared_atomic_float(const fs_builder &bld, case 32: case 64: - bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL, + bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, dest, srcs, SURFACE_LOGICAL_NUM_SRCS); break; default: diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index 1f5eb069e26..3873806ddd7 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -1492,7 +1492,6 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: /* Untyped Surface messages go through the data cache but the SFID value * changed on Haswell. */ @@ -1555,15 +1554,15 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) break; case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - desc = brw_dp_untyped_atomic_desc(devinfo, inst->exec_size, - lsc_op_to_legacy_atomic(arg.ud), - !inst->dst.is_null()); - break; - - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: - desc = brw_dp_untyped_atomic_float_desc(devinfo, inst->exec_size, - lsc_op_to_legacy_atomic(arg.ud), - !inst->dst.is_null()); + if (lsc_opcode_is_atomic_float((enum lsc_opcode) arg.ud)) { + desc = brw_dp_untyped_atomic_float_desc(devinfo, inst->exec_size, + lsc_op_to_legacy_atomic(arg.ud), + !inst->dst.is_null()); + } else { + desc = brw_dp_untyped_atomic_desc(devinfo, inst->exec_size, + lsc_op_to_legacy_atomic(arg.ud), + !inst->dst.is_null()); + } break; case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: @@ -1702,8 +1701,7 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) LSC_CACHE_STORE_L1STATE_L3MOCS, false /* has_dest */); break; - case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: { + case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: { /* Bspec: Atomic instruction -> Cache section: * * Atomic messages are always forced to "un-cacheable" in the L1 @@ -2703,7 +2701,6 @@ fs_visitor::lower_logical_sends() case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: if (devinfo->has_lsc) { diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index e0521d1647f..4412b366ae5 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -293,8 +293,6 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op) return "untyped_atomic"; case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: return "untyped_atomic_logical"; - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: - return "untyped_atomic_float_logical"; case VEC4_OPCODE_UNTYPED_SURFACE_READ: return "untyped_surface_read"; case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: @@ -1108,7 +1106,6 @@ backend_instruction::has_side_effects() const case BRW_OPCODE_SYNC: case VEC4_OPCODE_UNTYPED_ATOMIC: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_GFX4_SCRATCH_WRITE: case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
