Module: Mesa
Branch: main
Commit: 03ffb8d77c646c73fedef882605aac671d856718
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=03ffb8d77c646c73fedef882605aac671d856718

Author: Marek Olšák <[email protected]>
Date:   Sat Feb 18 03:39:42 2023 -0500

amd: update amdgpu_drm.h

>From kernel commit 817714d9665e.

Acked-by: Samuel Pitoiset <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21641>

---

 include/drm-uapi/amdgpu_drm.h | 10 ++++++++++
 src/amd/common/ac_gpu_info.c  | 10 ++++++++++
 2 files changed, 20 insertions(+)

diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index 45dc7e00c89..b6eb90df5d0 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -1116,6 +1116,16 @@ struct drm_amdgpu_info_device {
        __u64 tcc_disabled_mask;
        __u64 min_engine_clock;
        __u64 min_memory_clock;
+       /* The following fields are only set on gfx11+, older chips set 0. */
+       __u32 tcp_cache_size;       /* AKA GL0, VMEM cache */
+       __u32 num_sqc_per_wgp;
+       __u32 sqc_data_cache_size;  /* AKA SMEM cache */
+       __u32 sqc_inst_cache_size;
+       __u32 gl1c_cache_size;
+       __u32 gl2c_cache_size;
+       __u64 mall_size;            /* AKA infinity cache */
+       /* high 32 bits of the rb pipes mask */
+       __u32 enabled_rb_pipes_mask_hi;
 };
 
 struct drm_amdgpu_info_hw_ip {
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 5941fa828e7..ce382703d17 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -184,6 +184,16 @@ struct drm_amdgpu_info_device {
        uint64_t tcc_disabled_mask;
        uint64_t min_engine_clock;
        uint64_t min_memory_clock;
+       /* The following fields are only set on gfx11+, older chips set 0. */
+       uint32_t tcp_cache_size;       /* AKA GL0, VMEM cache */
+       uint32_t num_sqc_per_wgp;
+       uint32_t sqc_data_cache_size;  /* AKA SMEM cache */
+       uint32_t sqc_inst_cache_size;
+       uint32_t gl1c_cache_size;
+       uint32_t gl2c_cache_size;
+       uint64_t mall_size;            /* AKA infinity cache */
+       /* high 32 bits of the rb pipes mask */
+       uint32_t enabled_rb_pipes_mask_hi;
 };
 struct drm_amdgpu_info_hw_ip {
    uint32_t hw_ip_version_major;

Reply via email to