Module: Mesa Branch: main Commit: 0f045d43d615ade6197efe565ed9175f35686d47 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f045d43d615ade6197efe565ed9175f35686d47
Author: Bas Nieuwenhuizen <[email protected]> Date: Mon Mar 13 02:18:03 2023 +0100 ac/surface,radv: Opt out of stencil adjust. We never implemented it, and having broken mipmaps works out better for applications and CTS. Actually implementing stencil adjust is going to be a major pain due to stuff like the GENERAL layout. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21869> --- src/amd/common/ac_surface.c | 2 +- src/amd/common/ac_surface.h | 1 + src/amd/vulkan/radv_image.c | 17 +++++++++++++---- 3 files changed, 15 insertions(+), 5 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 9b568eee0d2..1c8fceccd2f 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1164,7 +1164,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i AddrSurfInfoIn.flags.matchStencilTileCfg = 1; /* Keep the depth mip-tail compatible with texturing. */ - if (config->info.levels > 1) + if (config->info.levels > 1 && !(surf->flags & RADEON_SURF_NO_STENCIL_ADJUST)) AddrSurfInfoIn.flags.noStencil = 1; } diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index c8d3da7325c..7be9a92dbd2 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -93,6 +93,7 @@ enum radeon_micro_mode * used as transfer resource. This flag indicates not to set flags.texture flag in * gfx9_compute_surface(). */ #define RADEON_SURF_NO_TEXTURE (1ull << 34) +#define RADEON_SURF_NO_STENCIL_ADJUST (1ull << 35) struct legacy_surf_level { uint32_t offset_256B; /* divided by 256, the hw can only do 40-bit addresses */ diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index d5f949957f8..d35553b8b62 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -624,10 +624,19 @@ radv_get_surface_flags(struct radv_device *device, struct radv_image *image, uns if (is_depth) { flags |= RADEON_SURF_ZBUFFER; - if (is_depth && is_stencil && - !(pCreateInfo->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT) && - device->physical_device->rad_info.gfx_level <= GFX8) - flags |= RADEON_SURF_NO_RENDER_TARGET; + if (is_depth && is_stencil && device->physical_device->rad_info.gfx_level <= GFX8) { + if (!(pCreateInfo->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) + flags |= RADEON_SURF_NO_RENDER_TARGET; + + /* RADV doesn't support stencil pitch adjustment. As a result there are some spec gaps that + * are not covered by CTS. + * + * For D+S images with pitch constraints due to rendertarget usage it can happen that + * sampling from mipmaps beyond the base level of the descriptor is broken as the pitch + * adjustment can't be applied to anything beyond the first level. + */ + flags |= RADEON_SURF_NO_STENCIL_ADJUST; + } if (radv_use_htile_for_image(device, image) && !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ) &&
