Module: Mesa Branch: main Commit: 2cf93f76322331176256881d510160ec4bcf718a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2cf93f76322331176256881d510160ec4bcf718a
Author: Lionel Landwerlin <[email protected]> Date: Tue Mar 7 12:11:25 2023 +0200 nir: add 2 new intel intrinsics for uniform ssbo/shared loads Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853> --- src/compiler/nir/nir_divergence_analysis.c | 2 ++ src/compiler/nir/nir_intrinsics.py | 9 +++++++++ src/compiler/nir/nir_opt_load_store_vectorize.c | 2 ++ 3 files changed, 13 insertions(+) diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index e70d1a8d1b5..639432e6771 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -206,6 +206,8 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_btd_shader_type_intel: case nir_intrinsic_load_base_workgroup_id: case nir_intrinsic_load_alpha_reference_amd: + case nir_intrinsic_load_ssbo_uniform_block_intel: + case nir_intrinsic_load_shared_uniform_block_intel: is_divergent = false; break; diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index fcb8a9885c0..7474afb87a8 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1754,6 +1754,15 @@ store("ssbo_block_intel", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET] # src[] = { value, offset }. store("shared_block_intel", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) +# Similar to load_global_const_block_intel but for SSBOs +# offset should be uniform +# src[] = { buffer_index, offset }. +load("ssbo_uniform_block_intel", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) + +# Similar to load_global_const_block_intel but for shared memory +# src[] = { offset }. +load("shared_uniform_block_intel", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) + # Intrinsics for Intel mesh shading system_value("mesh_inline_data_intel", 1, [ALIGN_OFFSET], bit_sizes=[32, 64]) diff --git a/src/compiler/nir/nir_opt_load_store_vectorize.c b/src/compiler/nir/nir_opt_load_store_vectorize.c index 802bcca21d8..7b8f5e449f8 100644 --- a/src/compiler/nir/nir_opt_load_store_vectorize.c +++ b/src/compiler/nir/nir_opt_load_store_vectorize.c @@ -156,6 +156,8 @@ case nir_intrinsic_##op: {\ ATOMIC(nir_var_mem_task_payload, task_payload, fcomp_swap, -1, 0, -1, 1) LOAD(nir_var_shader_temp, stack, -1, -1, -1) STORE(nir_var_shader_temp, stack, -1, -1, -1, 0) + LOAD(nir_var_mem_ssbo, ssbo_uniform_block_intel, 0, 1, -1) + LOAD(nir_var_mem_shared, shared_uniform_block_intel, -1, 0, -1) default: break; #undef ATOMIC
