Module: Mesa Branch: main Commit: 5e5ca30785a2c5538d04b714baae05db9a0eab32 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e5ca30785a2c5538d04b714baae05db9a0eab32
Author: Tapani Pälli <[email protected]> Date: Mon Apr 24 08:52:28 2023 +0300 iris: implement state cache invalidate for Wa_16013063087 Cc: mesa-stable Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651> --- src/gallium/drivers/iris/iris_state.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 0d539c82fd6..3717ed0ef54 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -660,6 +660,16 @@ emit_pipeline_select(struct iris_batch *batch, uint32_t pipeline) } else { flags |= PIPE_CONTROL_UNTYPED_DATAPORT_CACHE_FLUSH; } + /* Wa_16013063087 - State Cache Invalidate must be issued prior to + * PIPELINE_SELECT when switching from 3D to Compute. + * + * SW must do this by programming of PIPECONTROL with “CS Stall” followed + * by a PIPECONTROL with State Cache Invalidate bit set. + */ + if (pipeline == GPGPU && + intel_needs_workaround(batch->screen->devinfo, 16013063087)) + flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; + iris_emit_pipe_control_flush(batch, "PIPELINE_SELECT flush", flags); #else /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
