Module: Mesa Branch: main Commit: 72fc56aa37ab683b31731cdd6542071b1a047db3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=72fc56aa37ab683b31731cdd6542071b1a047db3
Author: Tapani Pälli <[email protected]> Date: Mon Apr 24 13:10:31 2023 +0300 anv: cleanup bitmask construction for PIPELINE_SELECT Cc: mesa-stable Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651> --- src/intel/vulkan/genX_cmd_buffer.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 6e5c913c68d..fe3f7e66567 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -6491,7 +6491,6 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, cmd_buffer->state.compute.pipeline_dirty = true; #endif - #if GFX_VERx10 < 125 /* We apparently cannot flush the tile cache (color/depth) from the GPGPU * pipeline. That means query clears will not be visible to query @@ -6506,6 +6505,9 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, } #endif + /* Flush and invalidate bits done needed prior PIPELINE_SELECT. */ + enum anv_pipe_bits bits = 0; + #if GFX_VER >= 12 /* From Tigerlake PRM, Volume 2a, PIPELINE_SELECT: * @@ -6521,8 +6523,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, * Note: Issuing PIPE_CONTROL_MEDIA_STATE_CLEAR causes GPU hangs, probably * because PIPE was not in MEDIA mode?! */ - enum anv_pipe_bits bits = ANV_PIPE_CS_STALL_BIT | - ANV_PIPE_HDC_PIPELINE_FLUSH_BIT; + bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_HDC_PIPELINE_FLUSH_BIT; if (cmd_buffer->state.current_pipeline == _3D) { bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | @@ -6530,7 +6531,6 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, } else { bits |= ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT; } - anv_add_pending_pipe_bits(cmd_buffer, bits, "flush PIPELINE_SELECT"); #else /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction] * PIPELINE_SELECT [DevBWR+]": @@ -6545,18 +6545,18 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, * Note the cmd_buffer_apply_pipe_flushes will split this into two * PIPE_CONTROLs. */ - anv_add_pending_pipe_bits(cmd_buffer, - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | - ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | - ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | - ANV_PIPE_CS_STALL_BIT | - ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | - ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | - ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | - ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | - ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT, - "flush and invalidate for PIPELINE_SELECT"); + bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | + ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | + ANV_PIPE_CS_STALL_BIT | + ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | + ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | + ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | + ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | + ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT; #endif + + anv_add_pending_pipe_bits(cmd_buffer, bits, "flush/invalidate PIPELINE_SELECT"); genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); #if GFX_VER == 9
