Module: Mesa Branch: main Commit: f53638fa1ac2d606729fa3095535243acff6b695 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f53638fa1ac2d606729fa3095535243acff6b695
Author: Nanley Chery <[email protected]> Date: Thu Apr 13 17:46:13 2023 -0700 iris: Enable MCS init with ISL_AUX_OP_AMBIGUATE Add support for using BLORP's ambiguate pass to initialize MCS instead of mapping and memsetting it on the CPU. Note that this won't be used if the first operation on the MSAA layer is a fast clear. Since we're no longer mapping, this removes a blocker towards getting MCS_CCS enabled in small-BAR mode. This functionality is difficult to test because of the way iris is set up. It always tries to compress writes. So, a test would only read the ambiguated MCS element if it tries to read from undefined samples. To test this, I locally disabled fast clears and rendering with MCS (via iris_resource_render_aux_usage). I continued to allow sampling with MCS in iris_resource_texture_aux_usage. So, writes go directly to the main surface and reads go through the ambiguated MCS surface. When I then ran the test group, dEQP-GLES3.functional.multisample.*, all 48/64 supported tests passed on my Ice Lake. If I slightly changed BLORP's ambiguate pass, I observed several tests failing. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545> --- src/gallium/drivers/iris/iris_resolve.c | 25 ++++++++++++++++--------- src/gallium/drivers/iris/iris_resource.c | 19 ++++--------------- 2 files changed, 20 insertions(+), 24 deletions(-) diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index 965259e9c0c..586df0599f5 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -537,11 +537,12 @@ iris_resolve_color(struct iris_context *ice, } static void -iris_mcs_partial_resolve(struct iris_context *ice, - struct iris_batch *batch, - struct iris_resource *res, - uint32_t start_layer, - uint32_t num_layers) +iris_mcs_exec(struct iris_context *ice, + struct iris_batch *batch, + struct iris_resource *res, + uint32_t start_layer, + uint32_t num_layers, + enum isl_aux_op op) { //DBG("%s to mt %p layers %u-%u\n", __func__, mt, //start_layer, start_layer + num_layers - 1); @@ -562,8 +563,15 @@ iris_mcs_partial_resolve(struct iris_context *ice, struct blorp_batch blorp_batch; iris_batch_sync_region_start(batch); blorp_batch_init(&ice->blorp, &blorp_batch, batch, 0); - blorp_mcs_partial_resolve(&blorp_batch, &surf, res->surf.format, - start_layer, num_layers); + + if (op == ISL_AUX_OP_PARTIAL_RESOLVE) { + blorp_mcs_partial_resolve(&blorp_batch, &surf, res->surf.format, + start_layer, num_layers); + } else { + assert(op == ISL_AUX_OP_AMBIGUATE); + blorp_mcs_ambiguate(&blorp_batch, &surf, start_layer, num_layers); + } + blorp_batch_finish(&blorp_batch); iris_batch_sync_region_end(batch); } @@ -846,8 +854,7 @@ iris_resource_prepare_access(struct iris_context *ice, if (aux_op == ISL_AUX_OP_NONE) { /* Nothing to do here. */ } else if (isl_aux_usage_has_mcs(res->aux.usage)) { - assert(aux_op == ISL_AUX_OP_PARTIAL_RESOLVE); - iris_mcs_partial_resolve(ice, batch, res, layer, 1); + iris_mcs_exec(ice, batch, res, layer, 1, aux_op); } else if (isl_aux_usage_has_hiz(res->aux.usage)) { iris_hiz_exec(ice, batch, res, level, layer, 1, aux_op, false); } else if (res->aux.usage == ISL_AUX_USAGE_STC_CCS) { diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c index ff3318d4903..1087649f99e 100644 --- a/src/gallium/drivers/iris/iris_resource.c +++ b/src/gallium/drivers/iris/iris_resource.c @@ -866,20 +866,12 @@ iris_resource_configure_aux(struct iris_screen *screen, case ISL_AUX_USAGE_HIZ: case ISL_AUX_USAGE_HIZ_CCS: case ISL_AUX_USAGE_HIZ_CCS_WT: - initial_state = ISL_AUX_STATE_AUX_INVALID; - break; case ISL_AUX_USAGE_MCS: case ISL_AUX_USAGE_MCS_CCS: - /* The Ivybridge PRM, Vol 2 Part 1 p326 says: - * - * "When MCS buffer is enabled and bound to MSRT, it is required - * that it is cleared prior to any rendering." - * - * Since we only use the MCS buffer for rendering, we just clear it - * immediately on allocation. The clear value for MCS buffers is all - * 1's, so we simply memset it to 0xff. + /* Leave the auxiliary buffer uninitialized. We can ambiguate it before + * accessing it later on, if needed. */ - initial_state = ISL_AUX_STATE_CLEAR; + initial_state = ISL_AUX_STATE_AUX_INVALID; break; case ISL_AUX_USAGE_CCS_D: case ISL_AUX_USAGE_CCS_E: @@ -950,10 +942,7 @@ iris_resource_init_aux_buf(struct iris_screen *screen, if (!map) return false; - /* See iris_resource_configure_aux for the memset_value rationale. */ - uint8_t memset_value = isl_aux_usage_has_mcs(res->aux.usage) ? 0xFF : 0; - memset((char*)map + res->aux.offset, memset_value, - res->aux.surf.size_B); + memset((char*)map + res->aux.offset, 0, res->aux.surf.size_B); } if (res->aux.extra_aux.surf.size_B > 0) {
