Module: Mesa Branch: main Commit: 48b32124c61f35ef39cee7e32ff7795dd49e0690 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=48b32124c61f35ef39cee7e32ff7795dd49e0690
Author: Konstantin Seurer <[email protected]> Date: Tue Jun 20 18:19:57 2023 +0200 radv/rt: Store the prolog outside the shaders array Avoids including it in executable statistics queries. Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23524> --- src/amd/vulkan/radv_cmd_buffer.c | 2 +- src/amd/vulkan/radv_pipeline_compute.c | 15 +++++++-------- src/amd/vulkan/radv_pipeline_rt.c | 10 +++++----- src/amd/vulkan/radv_private.h | 4 +++- 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 011c7a74077..a1a35762914 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -6512,7 +6512,7 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint); radv_bind_shader(cmd_buffer, rt_pipeline->base.base.shaders[MESA_SHADER_INTERSECTION], MESA_SHADER_INTERSECTION); - cmd_buffer->state.rt_prolog = rt_pipeline->base.base.shaders[MESA_SHADER_COMPUTE]; + cmd_buffer->state.rt_prolog = rt_pipeline->prolog; cmd_buffer->state.rt_pipeline = rt_pipeline; cmd_buffer->push_constant_stages |= RADV_RT_STAGE_BITS; diff --git a/src/amd/vulkan/radv_pipeline_compute.c b/src/amd/vulkan/radv_pipeline_compute.c index bbd5f6fb2d5..0f0fb9aae8c 100644 --- a/src/amd/vulkan/radv_pipeline_compute.c +++ b/src/amd/vulkan/radv_pipeline_compute.c @@ -97,10 +97,10 @@ radv_pipeline_emit_compute_state(const struct radv_physical_device *pdevice, str } static void -radv_compute_generate_pm4(const struct radv_device *device, struct radv_compute_pipeline *pipeline) +radv_compute_generate_pm4(const struct radv_device *device, struct radv_compute_pipeline *pipeline, + struct radv_shader *shader) { struct radv_physical_device *pdevice = device->physical_device; - struct radv_shader *shader = pipeline->base.shaders[MESA_SHADER_COMPUTE]; struct radeon_cmdbuf *cs = &pipeline->base.cs; cs->reserved_dw = cs->max_dw = pdevice->rad_info.gfx_level >= GFX10 ? 19 : 16; @@ -134,18 +134,17 @@ radv_generate_compute_pipeline_key(const struct radv_device *device, struct radv void radv_compute_pipeline_init(const struct radv_device *device, struct radv_compute_pipeline *pipeline, - const struct radv_pipeline_layout *layout) + const struct radv_pipeline_layout *layout, struct radv_shader *shader) { - pipeline->base.need_indirect_descriptor_sets |= - radv_shader_need_indirect_descriptor_sets(pipeline->base.shaders[MESA_SHADER_COMPUTE]); + pipeline->base.need_indirect_descriptor_sets |= radv_shader_need_indirect_descriptor_sets(shader); radv_pipeline_init_scratch(device, &pipeline->base); pipeline->base.push_constant_size = layout->push_constant_size; pipeline->base.dynamic_offset_count = layout->dynamic_offset_count; - pipeline->base.shader_upload_seq = pipeline->base.shaders[MESA_SHADER_COMPUTE]->upload_seq; + pipeline->base.shader_upload_seq = shader->upload_seq; - radv_compute_generate_pm4(device, pipeline); + radv_compute_generate_pm4(device, pipeline, shader); } static VkResult @@ -290,7 +289,7 @@ radv_compute_pipeline_create(VkDevice _device, VkPipelineCache _cache, const VkC return result; } - radv_compute_pipeline_init(device, pipeline, pipeline_layout); + radv_compute_pipeline_init(device, pipeline, pipeline_layout, pipeline->base.shaders[MESA_SHADER_COMPUTE]); *pPipeline = radv_pipeline_to_handle(&pipeline->base); radv_rmv_log_compute_pipeline_create(device, pCreateInfo->flags, &pipeline->base, pipeline->base.is_internal); diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c index 5a0d6cafdc3..7f9a4f3a469 100644 --- a/src/amd/vulkan/radv_pipeline_rt.c +++ b/src/amd/vulkan/radv_pipeline_rt.c @@ -504,10 +504,10 @@ postprocess_rt_config(struct ac_shader_config *config, enum amd_gfx_level gfx_le static void compile_rt_prolog(struct radv_device *device, struct radv_ray_tracing_pipeline *pipeline) { - pipeline->base.base.shaders[MESA_SHADER_COMPUTE] = radv_create_rt_prolog(device); + pipeline->prolog = radv_create_rt_prolog(device); /* create combined config */ - struct ac_shader_config *config = &pipeline->base.base.shaders[MESA_SHADER_COMPUTE]->config; + struct ac_shader_config *config = &pipeline->prolog->config; for (unsigned i = 0; i < pipeline->stage_count; i++) { if (radv_ray_tracing_stage_is_compiled(&pipeline->stages[i])) { struct radv_shader *shader = container_of(pipeline->stages[i].shader, struct radv_shader, base); @@ -576,7 +576,7 @@ radv_rt_pipeline_create(VkDevice _device, VkPipelineCache _cache, const VkRayTra compute_rt_stack_size(pCreateInfo, pipeline); compile_rt_prolog(device, pipeline); - radv_compute_pipeline_init(device, &pipeline->base, pipeline_layout); + radv_compute_pipeline_init(device, &pipeline->base, pipeline_layout, pipeline->prolog); radv_rmv_log_compute_pipeline_create(device, pCreateInfo->flags, &pipeline->base.base, false); } @@ -611,8 +611,8 @@ radv_destroy_ray_tracing_pipeline(struct radv_device *device, struct radv_ray_tr vk_pipeline_cache_object_unref(&device->vk, pipeline->stages[i].shader); } - if (pipeline->base.base.shaders[MESA_SHADER_COMPUTE]) - radv_shader_unref(device, pipeline->base.base.shaders[MESA_SHADER_COMPUTE]); + if (pipeline->prolog) + radv_shader_unref(device, pipeline->prolog); if (pipeline->base.base.shaders[MESA_SHADER_INTERSECTION]) radv_shader_unref(device, pipeline->base.base.shaders[MESA_SHADER_INTERSECTION]); } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index f52a39b3855..3db641be8bb 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2315,6 +2315,8 @@ radv_ray_tracing_stage_is_compiled(struct radv_ray_tracing_stage *stage) struct radv_ray_tracing_pipeline { struct radv_compute_pipeline base; + struct radv_shader *prolog; + struct radv_ray_tracing_stage *stages; struct radv_ray_tracing_group *groups; unsigned stage_count; @@ -2404,7 +2406,7 @@ bool radv_mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsi nir_intrinsic_instr *low, nir_intrinsic_instr *high, void *data); void radv_compute_pipeline_init(const struct radv_device *device, struct radv_compute_pipeline *pipeline, - const struct radv_pipeline_layout *layout); + const struct radv_pipeline_layout *layout, struct radv_shader *shader); struct radv_graphics_pipeline_create_info { bool use_rectlist;
