Module: Mesa Branch: main Commit: 46e1a2b31e04ebd02c3471308521f39335c0c173 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=46e1a2b31e04ebd02c3471308521f39335c0c173
Author: Jordan Justen <[email protected]> Date: Mon May 15 14:53:03 2023 -0400 iris: Flush untyped dataport cache when HDC flush is requested on compute In the Intel(R) Arc(tm) A-Series Graphics and Intel Data Center GPU Flex Series Open-Source Programmer's Reference Manual, Vol 2a: Command Reference: Instructions, PIPE_CONTROL, HDC Pipeline Flush (DWord 0, Bit 9), there is a programming note: > When the "Pipeline Select" mode is set to "GPGPU", the LSC Untyped > L1 cache flush is controlled by "Untyped Data-Port Cache Flush" bit > in the PIPE_CONTROL command. Ref: bd8e8d204db ("iris: Add missing untyped data port flush on PIPELINE_SELECT") Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23176> --- src/gallium/drivers/iris/iris_state.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 86e9d8cdafb..cc949b31ff4 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -8826,7 +8826,8 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, #endif #if GFX_VERx10 >= 125 pc.UntypedDataPortCacheFlushEnable = - (flags & PIPE_CONTROL_UNTYPED_DATAPORT_CACHE_FLUSH) && + (flags & (PIPE_CONTROL_UNTYPED_DATAPORT_CACHE_FLUSH | + PIPE_CONTROL_FLUSH_HDC)) && IS_COMPUTE_PIPELINE(batch); pc.HDCPipelineFlushEnable |= pc.UntypedDataPortCacheFlushEnable; pc.CCSFlushEnable |= flags & PIPE_CONTROL_CCS_CACHE_FLUSH;
