Module: Mesa Branch: main Commit: a831ee51ae6e522295c68a9af7659c9edf9258a8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a831ee51ae6e522295c68a9af7659c9edf9258a8
Author: Jordan Justen <[email protected]> Date: Mon May 15 14:53:03 2023 -0400 anv: Flush untyped dataport cache DC flush is requested on compute Although the following is based on this observations for OpenGL, we probably need this for Vulkan as well. KHR-GL46.texture_buffer.texture_buffer_operations_ssbo_writes writes to an SSBO in a compute program, then issues a memory-barrier, which causes us to add a DC-flush. Then a second compute program samples from the SSBO written by the first compute program. Although we expected the DC-flush to make the writes available to the second compute program, on MTL this wasn't the case. Adding the "Untyped Data-Port Cache Flush" fixes this. The PRM indicates that compute programs must set "Untyped Data-Port Cache Flush" to flush some LSC writes when flushing HDC. Although we are setting DC-flush, and not HDC-flush, it does appear that the following reference might also apply to DC-flush. In the Intel(R) Arc(tm) A-Series Graphics and Intel Data Center GPU Flex Series Open-Source Programmer's Reference Manual, Vol 2a: Command Reference: Instructions, PIPE_CONTROL, HDC Pipeline Flush (DWord 0, Bit 9), there is a programming note: > When the "Pipeline Select" mode is set to "GPGPU", the LSC Untyped > L1 cache flush is controlled by "Untyped Data-Port Cache Flush" bit > in the PIPE_CONTROL command. Ref: a8108f1d444 ("anv: Add missing untyped data port flush on PIPELINE_SELECT") Ref: bd8e8d204db ("iris: Add missing untyped data port flush on PIPELINE_SELECT") Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23176> --- src/intel/vulkan/genX_cmd_buffer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index b3862f88fba..48f23380ea3 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1561,7 +1561,8 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, if (current_pipeline != GPGPU) { flush_bits &= ~ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT; } else { - if (flush_bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT) + if (flush_bits & (ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | + ANV_PIPE_DATA_CACHE_FLUSH_BIT)) flush_bits |= ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT; }
