Module: Mesa Branch: main Commit: 215c6c6ce4c82c897ef87d06fb685ed01ee5b8ab URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=215c6c6ce4c82c897ef87d06fb685ed01ee5b8ab
Author: Jordan Justen <[email protected]> Date: Mon May 15 14:53:03 2023 -0400 anv: Flush untyped dataport cache when HDC flush is requested on compute In the Intel(R) Arc(tm) A-Series Graphics and Intel Data Center GPU Flex Series Open-Source Programmer's Reference Manual, Vol 2a: Command Reference: Instructions, PIPE_CONTROL, HDC Pipeline Flush (DWord 0, Bit 9), there is a programming note: > When the "Pipeline Select" mode is set to "GPGPU", the LSC Untyped > L1 cache flush is controlled by "Untyped Data-Port Cache Flush" bit > in the PIPE_CONTROL command. Ref: a8108f1d444 ("anv: Add missing untyped data port flush on PIPELINE_SELECT") Ref: bd8e8d204db ("iris: Add missing untyped data port flush on PIPELINE_SELECT") Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23176> --- src/intel/vulkan/genX_cmd_buffer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 6d1da689339..b3862f88fba 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1560,6 +1560,9 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, */ if (current_pipeline != GPGPU) { flush_bits &= ~ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT; + } else { + if (flush_bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT) + flush_bits |= ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT; } if (flush_bits & ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT)
