Module: Mesa Branch: main Commit: da28582eec47c029e5251c437c84f6023a81777e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=da28582eec47c029e5251c437c84f6023a81777e
Author: Francisco Jerez <curroje...@riseup.net> Date: Fri Sep 29 14:13:57 2023 -0700 intel/xehp+: Add dynamic state flags controlling whether TBIMR is enabled during 3D primitives. Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493> --- src/gallium/drivers/iris/iris_context.h | 2 ++ src/gallium/drivers/iris/iris_state.c | 4 +++- src/intel/blorp/blorp_genX_exec.h | 5 +++++ src/intel/vulkan/anv_private.h | 2 ++ src/intel/vulkan/genX_cmd_buffer.c | 21 +++++++++++++++++++++ 5 files changed, 33 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index c5bfdf1e4d4..cefc62a82fc 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -914,6 +914,8 @@ struct iris_context { /** Resource holding the pixel pipe hashing tables. */ struct pipe_resource *pixel_hashing_tables; + + bool use_tbimr; } state; }; diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index c13ed9e9cf1..28e293e79ec 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -7981,7 +7981,9 @@ iris_upload_render_state(struct iris_context *ice, iris_emit_cmd(batch, GENX(3DPRIMITIVE), prim) { prim.VertexAccessType = draw->index_size > 0 ? RANDOM : SEQUENTIAL; prim.PredicateEnable = use_predicate; - +#if GFX_VERx10 >= 125 + prim.TBIMREnable = ice->state.use_tbimr; +#endif if (indirect) { prim.IndirectParameterEnable = true; } else { diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 70aa7584ce9..83381eec959 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -2047,12 +2047,17 @@ blorp_exec_3d(struct blorp_batch *batch, const struct blorp_params *params) if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL)) blorp_emit_depth_stencil_config(batch, params); + const UNUSED bool use_tbimr = false; + blorp_emit_breakpoint_pre_draw(batch); blorp_emit(batch, GENX(3DPRIMITIVE), prim) { prim.VertexAccessType = SEQUENTIAL; prim.PrimitiveTopologyType = _3DPRIM_RECTLIST; #if GFX_VER >= 7 prim.PredicateEnable = batch->flags & BLORP_BATCH_PREDICATE_ENABLE; +#endif +#if GFX_VERx10 >= 125 + prim.TBIMREnable = use_tbimr; #endif prim.VertexCountPerInstance = 3; prim.InstanceCount = params->num_layers; diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 15a746126ab..af03235a90a 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -1429,6 +1429,8 @@ struct anv_gfx_dynamic_state { uint32_t BackfaceStencilTestFunction; } ds; + bool use_tbimr; + bool pma_fix; BITSET_DECLARE(dirty, ANV_GFX_STATE_MAX); diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 5dc62e8fb04..fa3f1415951 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -4221,6 +4221,9 @@ void genX(CmdDraw)( anv_batch_emit(&cmd_buffer->batch, _3DPRIMITIVE_DIRECT, prim) { prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled; +#if GFX_VERx10 >= 125 + prim.TBIMREnable = cmd_buffer->state.gfx.dyn_state.use_tbimr; +#endif prim.VertexAccessType = SEQUENTIAL; prim.VertexCountPerInstance = vertexCount; prim.StartVertexLocation = firstVertex; @@ -4316,6 +4319,9 @@ void genX(CmdDrawMultiEXT)( genX(emit_breakpoint)(&cmd_buffer->batch, cmd_buffer->device, true); anv_batch_emit(&cmd_buffer->batch, _3DPRIMITIVE_DIRECT, prim) { +#if GFX_VERx10 >= 125 + prim.TBIMREnable = cmd_buffer->state.gfx.dyn_state.use_tbimr; +#endif prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled; prim.VertexAccessType = SEQUENTIAL; prim.VertexCountPerInstance = draw->vertexCount; @@ -4385,6 +4391,9 @@ void genX(CmdDrawIndexed)( anv_batch_emit(&cmd_buffer->batch, _3DPRIMITIVE_DIRECT, prim) { prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled; +#if GFX_VERx10 >= 125 + prim.TBIMREnable = cmd_buffer->state.gfx.dyn_state.use_tbimr; +#endif prim.VertexAccessType = RANDOM; prim.VertexCountPerInstance = indexCount; prim.StartVertexLocation = firstIndex; @@ -4562,6 +4571,9 @@ void genX(CmdDrawMultiIndexedEXT)( genX(emit_breakpoint)(&cmd_buffer->batch, cmd_buffer->device, true); anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE_EXTENDED), prim) { +#if GFX_VERx10 >= 125 + prim.TBIMREnable = cmd_buffer->state.gfx.dyn_state.use_tbimr; +#endif prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled; prim.VertexAccessType = RANDOM; prim.VertexCountPerInstance = draw->indexCount; @@ -4687,6 +4699,9 @@ void genX(CmdDrawIndirectByteCountEXT)( genX(emit_breakpoint)(&cmd_buffer->batch, cmd_buffer->device, true); anv_batch_emit(&cmd_buffer->batch, _3DPRIMITIVE_DIRECT, prim) { +#if GFX_VERx10 >= 125 + prim.TBIMREnable = cmd_buffer->state.gfx.dyn_state.use_tbimr; +#endif prim.IndirectParameterEnable = true; prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled; prim.VertexAccessType = SEQUENTIAL; @@ -4816,6 +4831,9 @@ emit_indirect_draws(struct anv_cmd_buffer *cmd_buffer, genX(emit_breakpoint)(&cmd_buffer->batch, cmd_buffer->device, true); anv_batch_emit(&cmd_buffer->batch, _3DPRIMITIVE_DIRECT, prim) { +#if GFX_VERx10 >= 125 + prim.TBIMREnable = cmd_buffer->state.gfx.dyn_state.use_tbimr; +#endif prim.IndirectParameterEnable = true; prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled; prim.VertexAccessType = indexed ? RANDOM : SEQUENTIAL; @@ -5040,6 +5058,9 @@ emit_indirect_count_draws(struct anv_cmd_buffer *cmd_buffer, genX(emit_breakpoint)(&cmd_buffer->batch, cmd_buffer->device, true); anv_batch_emit(&cmd_buffer->batch, _3DPRIMITIVE_DIRECT, prim) { +#if GFX_VERx10 >= 125 + prim.TBIMREnable = cmd_buffer->state.gfx.dyn_state.use_tbimr; +#endif prim.IndirectParameterEnable = true; prim.PredicateEnable = true; prim.VertexAccessType = indexed ? RANDOM : SEQUENTIAL;
