Module: Mesa Branch: main Commit: f0d24b155b5c434b59e9431809633cee6e7e49de URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0d24b155b5c434b59e9431809633cee6e7e49de
Author: Francisco Jerez <curroje...@riseup.net> Date: Fri Oct 20 14:23:12 2023 -0700 intel/xehp+: Adjust TBIMR batch size based on slice count. This programs a TBIMR batch size equal to 128 polygons per slice in order to match the hardware spec recommendation (BSpec 68436). This has been confirmed to improve performance slightly relative to the hardware default batch size of 256 polygons. Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493> --- src/gallium/drivers/iris/iris_state.c | 9 +++++++++ src/intel/genxml/gen125.xml | 2 ++ src/intel/vulkan/genX_gfx_state.c | 8 ++++++++ src/intel/vulkan/genX_init_state.c | 2 ++ 4 files changed, 21 insertions(+) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 70f08ae72c9..e0e540e12e3 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -1312,8 +1312,10 @@ iris_init_render_context(struct iris_batch *batch) #if GFX_VERx10 == 125 iris_emit_reg(batch, GENX(CHICKEN_RASTER_2), reg) { + reg.TBIMRBatchSizeOverride = true; reg.TBIMROpenBatchEnable = true; reg.TBIMRFastClip = true; + reg.TBIMRBatchSizeOverrideMask = true; reg.TBIMROpenBatchEnableMask = true; reg.TBIMRFastClipMask = true; }; @@ -6754,11 +6756,18 @@ iris_upload_dirty_render_state(struct iris_context *ice, calculate_tile_dimensions(ice, &tile_width, &tile_height); if (ice->state.use_tbimr) { + /* Use a batch size of 128 polygons per slice as recommended + * by BSpec 68436 "TBIMR Programming". + */ + const unsigned num_slices = screen->devinfo->num_slices; + const unsigned batch_size = DIV_ROUND_UP(num_slices, 2) * 256; + iris_emit_cmd(batch, GENX(3DSTATE_TBIMR_TILE_PASS_INFO), tbimr) { tbimr.TileRectangleHeight = tile_height; tbimr.TileRectangleWidth = tile_width; tbimr.VerticalTileCount = DIV_ROUND_UP(cso_fb->height, tile_height); tbimr.HorizontalTileCount = DIV_ROUND_UP(cso_fb->width, tile_width); + tbimr.TBIMRBatchSize = util_logbase2(batch_size) - 5; } } } diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml index 4758086b928..a0e89eec409 100644 --- a/src/intel/genxml/gen125.xml +++ b/src/intel/genxml/gen125.xml @@ -2029,8 +2029,10 @@ <field name="AA Line Quality Fix Mask" start="21" end="21" type="bool" /> </register> <register name="CHICKEN_RASTER_2" length="1" num="0x6208"> + <field name="TBIMR Batch Size Override" start="1" end="1" type="bool" /> <field name="TBIMR Open Batch Enable" start="4" end="4" type="bool" /> <field name="TBIMR Fast Clip" start="5" end="5" type="bool" /> + <field name="TBIMR Batch Size Override Mask" start="17" end="17" type="bool" /> <field name="TBIMR Open Batch Enable Mask" start="20" end="20" type="bool" /> <field name="TBIMR Fast Clip Mask" start="21" end="21" type="bool" /> </register> diff --git a/src/intel/vulkan/genX_gfx_state.c b/src/intel/vulkan/genX_gfx_state.c index cec6177808b..c3d791268cd 100644 --- a/src/intel/vulkan/genX_gfx_state.c +++ b/src/intel/vulkan/genX_gfx_state.c @@ -1266,12 +1266,20 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer) calculate_render_area(cmd_buffer, &fb_width, &fb_height) && calculate_tile_dimensions(cmd_buffer, fb_width, fb_height, &tile_width, &tile_height)) { + /* Use a batch size of 128 polygons per slice as recommended + * by BSpec 68436 "TBIMR Programming". + */ + const unsigned num_slices = cmd_buffer->device->info->num_slices; + const unsigned batch_size = DIV_ROUND_UP(num_slices, 2) * 256; + SET(TBIMR_TILE_PASS_INFO, tbimr.TileRectangleHeight, tile_height); SET(TBIMR_TILE_PASS_INFO, tbimr.TileRectangleWidth, tile_width); SET(TBIMR_TILE_PASS_INFO, tbimr.VerticalTileCount, DIV_ROUND_UP(fb_height, tile_height)); SET(TBIMR_TILE_PASS_INFO, tbimr.HorizontalTileCount, DIV_ROUND_UP(fb_width, tile_width)); + SET(TBIMR_TILE_PASS_INFO, tbimr.TBIMRBatchSize, + util_logbase2(batch_size) - 5); SET(TBIMR_TILE_PASS_INFO, use_tbimr, true); } else { hw_state->use_tbimr = false; diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c index caa4d1251a9..96254cece89 100644 --- a/src/intel/vulkan/genX_init_state.c +++ b/src/intel/vulkan/genX_init_state.c @@ -544,8 +544,10 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch) #if GFX_VERx10 == 125 anv_batch_write_reg(&batch, GENX(CHICKEN_RASTER_2), reg) { + reg.TBIMRBatchSizeOverride = true; reg.TBIMROpenBatchEnable = true; reg.TBIMRFastClip = true; + reg.TBIMRBatchSizeOverrideMask = true; reg.TBIMROpenBatchEnableMask = true; reg.TBIMRFastClipMask = true; }
