Module: Mesa Branch: main Commit: ad4b82e1920401acd83cda3f6d081d38c221ae78 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad4b82e1920401acd83cda3f6d081d38c221ae78
Author: Tatsuyuki Ishi <ishitatsuy...@gmail.com> Date: Sat Nov 11 18:11:08 2023 +0900 radv: Pre-mask misaligned_mask for VS prolog. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023> --- src/amd/vulkan/radv_cmd_buffer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index a1ced57bd15..014d197fdda 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3749,6 +3749,7 @@ lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v cmd_buffer->state.vbo_misaligned_mask_invalid &= ~attribute_mask; } misaligned_mask |= state->nontrivial_formats; + misaligned_mask &= attribute_mask; const bool can_use_simple_input = cmd_buffer->state.shaders[MESA_SHADER_VERTEX] && @@ -3778,7 +3779,7 @@ lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v key.nontrivial_divisors = *nontrivial_divisors; key.zero_divisors = zero_divisors; /* If the attribute is aligned, post shuffle is implemented using DST_SEL instead. */ - key.post_shuffle = state->post_shuffle & attribute_mask & misaligned_mask; + key.post_shuffle = state->post_shuffle & misaligned_mask; key.alpha_adjust_hi = state->alpha_adjust_hi & attribute_mask; key.alpha_adjust_lo = state->alpha_adjust_lo & attribute_mask; u_foreach_bit (index, misaligned_mask)
