Module: Mesa Branch: main Commit: 4f41c44df22116d351d06c3a03711e8ee68a7869 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f41c44df22116d351d06c3a03711e8ee68a7869
Author: Sviatoslav Peleshko <sviatoslav.peles...@globallogic.com> Date: Mon Oct 9 12:48:02 2023 +0300 intel/compiler: Add variable to dump binaries of all compiled shaders This can be useful for testing i965_disasm and i965_asm by comparing bin -> asm -> bin results. Signed-off-by: Sviatoslav Peleshko <sviatoslav.peles...@globallogic.com> Reviewed-by: Sagar Ghuge <sagar.gh...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657> --- docs/envvars.rst | 13 +++++++++ src/intel/compiler/brw_eu.c | 45 +++++++++++++++++++++++++++++++ src/intel/compiler/brw_eu.h | 4 +++ src/intel/compiler/brw_fs_generator.cpp | 13 ++++++--- src/intel/compiler/brw_vec4_generator.cpp | 12 ++++++--- 5 files changed, 81 insertions(+), 6 deletions(-) diff --git a/docs/envvars.rst b/docs/envvars.rst index d466755d0f0..300f2cd40e1 100644 --- a/docs/envvars.rst +++ b/docs/envvars.rst @@ -753,6 +753,19 @@ Intel driver environment variables overrode shader with sha1 <SHA-1>" in stderr replacing the original assembly. +.. envvar:: INTEL_SHADER_BIN_DUMP_PATH + + if set, determines the directory to which the compiled shaders will be + dumped. They will be dumped as ``sha1_of_assembly.bin``, where the sha1 + values will be the same as can be found in the :envvar:`INTEL_DEBUG` + output, and can be used for :envvar:`INTEL_SHADER_ASM_READ_PATH` input. + + .. note:: + Unlike the text form of shader dumping, :envvar:`INTEL_DEBUG` + does not affect on the list of shaders to dump. All generated shaders + are always dumped if :envvar:`INTEL_SHADER_BIN_DUMP_PATH` variable is + set. + .. envvar:: INTEL_SIMD_DEBUG a comma-separated list of named flags, which control simd dispatch widths: diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c index e865300a5c0..fb493e8ac4d 100644 --- a/src/intel/compiler/brw_eu.c +++ b/src/intel/compiler/brw_eu.c @@ -38,6 +38,7 @@ #include "brw_gfx_ver_enum.h" #include "dev/intel_debug.h" +#include "util/u_debug.h" #include "util/ralloc.h" /* Returns a conditional modifier that negates the condition. */ @@ -371,6 +372,50 @@ brw_get_shader_relocs(struct brw_codegen *p, unsigned *num_relocs) return p->relocs; } +DEBUG_GET_ONCE_OPTION(shader_bin_dump_path, "INTEL_SHADER_BIN_DUMP_PATH", NULL); + +bool brw_should_dump_shader_bin(void) +{ + return debug_get_option_shader_bin_dump_path() != NULL; +} + +void brw_dump_shader_bin(void *assembly, int start_offset, int end_offset, + const char *identifier) +{ + char *name = ralloc_asprintf(NULL, "%s/%s.bin", + debug_get_option_shader_bin_dump_path(), + identifier); + + int fd = open(name, O_CREAT | O_WRONLY, 0777); + ralloc_free(name); + + if (fd < 0) + return; + + struct stat sb; + if (fstat(fd, &sb) != 0 || (!S_ISREG(sb.st_mode))) { + close(fd); + return; + } + + size_t to_write = end_offset - start_offset; + void *write_ptr = assembly + start_offset; + + while (to_write) { + ssize_t ret = write(fd, write_ptr, to_write); + + if (ret <= 0) { + close(fd); + return; + } + + to_write -= ret; + write_ptr += ret; + } + + close(fd); +} + bool brw_try_override_assembly(struct brw_codegen *p, int start_offset, const char *identifier) { diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index 154ec4c9e7a..0426fc80c0d 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -197,6 +197,10 @@ const struct brw_shader_reloc *brw_get_shader_relocs(struct brw_codegen *p, unsigned *num_relocs); const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz ); +bool brw_should_dump_shader_bin(void); +void brw_dump_shader_bin(void *assembly, int start_offset, int end_offset, + const char *identifier); + bool brw_try_override_assembly(struct brw_codegen *p, int start_offset, const char *identifier); diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 53b966f01ec..a3481d159c3 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -2400,14 +2400,21 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, brw_compact_instructions(p, start_offset, disasm_info); int after_size = p->next_insn_offset - start_offset; - if (unlikely(debug_flag)) { - unsigned char sha1[21]; - char sha1buf[41]; + bool dump_shader_bin = brw_should_dump_shader_bin(); + unsigned char sha1[21]; + char sha1buf[41]; + if (unlikely(debug_flag || dump_shader_bin)) { _mesa_sha1_compute(p->store + start_offset / sizeof(brw_inst), after_size, sha1); _mesa_sha1_format(sha1buf, sha1); + } + if (unlikely(dump_shader_bin)) + brw_dump_shader_bin(p->store, start_offset, p->next_insn_offset, + sha1buf); + + if (unlikely(debug_flag)) { fprintf(stderr, "Native code for %s (src_hash 0x%08x) (sha1 %s)\n" "SIMD%d shader: %d instructions. %d loops. %u cycles. " "%d:%d spills:fills, %u sends, " diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index 80fae117a90..a62ca3df242 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -2231,13 +2231,19 @@ generate_code(struct brw_codegen *p, brw_compact_instructions(p, 0, disasm_info); int after_size = p->next_insn_offset; - if (unlikely(debug_enabled)) { - unsigned char sha1[21]; - char sha1buf[41]; + bool dump_shader_bin = brw_should_dump_shader_bin(); + unsigned char sha1[21]; + char sha1buf[41]; + if (unlikely(debug_enabled || dump_shader_bin)) { _mesa_sha1_compute(p->store, p->next_insn_offset, sha1); _mesa_sha1_format(sha1buf, sha1); + } + if (unlikely(dump_shader_bin)) + brw_dump_shader_bin(p->store, 0, p->next_insn_offset, sha1buf); + + if (unlikely(debug_enabled)) { fprintf(stderr, "Native code for %s %s shader %s (src_hash 0x%08x) (sha1 %s):\n", nir->info.label ? nir->info.label : "unnamed", _mesa_shader_stage_to_string(nir->info.stage), nir->info.name,
