Module: Mesa
Branch: main
Commit: bb2083a57ccca93254ca4cb8ab7f3cedc56d8d94
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb2083a57ccca93254ca4cb8ab7f3cedc56d8d94
Author: Sviatoslav Peleshko <sviatoslav.peles...@globallogic.com>
Date: Wed Oct 11 13:37:40 2023 +0300
intel/tools/tests: Fix sends indirect argument in gfx9 test
Currently it's in the wrong format. It was fixed in disasm in
98aab272 ("intel/disasm: Properly disassemble indirect SENDs").
This was accidentally working previously, but isn't accepted after the
changes made to implement send on gfx12.
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peles...@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.gh...@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
---
src/intel/tools/tests/gen9/sends.asm | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/tools/tests/gen9/sends.asm
b/src/intel/tools/tests/gen9/sends.asm
index b803f4fce40..9f7c8505c9c 100644
--- a/src/intel/tools/tests/gen9/sends.asm
+++ b/src/intel/tools/tests/gen9/sends.asm
@@ -70,7 +70,7 @@ sends(8) g11UD g25UD g26UD
0x0210b4fe
dp data 1 MsgDesc: ( DC untyped atomic op, Surface
= 254, SIMD8, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
sends(16) g1UD g14UD g16UD 0x0420a7fe
0x00000080
dp data 1 MsgDesc: ( DC untyped atomic op, Surface
= 254, SIMD16, add) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
-(+f1.0) sends(8) nullUD g2UD g13UD g[a0]UD
0x00000100
+(+f1.0) sends(8) nullUD g2UD g13UD a0<0>UD
0x00000100
dp data 1 MsgDesc: indirect ex_mlen 4 {
align1 1Q };
(+f1.0) sends(8) nullUD g5UD g6UD 0x02026e01
0x00000040
dp data 1 MsgDesc: ( DC untyped surface write,
Surface = 1, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
