Module: Mesa Branch: main Commit: 3a776f036fc9d47f9afaf6003f256f098ef934a1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a776f036fc9d47f9afaf6003f256f098ef934a1
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com> Date: Tue Jan 9 14:43:23 2024 +0100 radv: use radv_shader_stage_key directly with pre-existing fields More fields will be moved to radv_shader_stage_key but start using it with pre-existing fields. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007> --- src/amd/vulkan/radv_pipeline.c | 4 ++-- src/amd/vulkan/radv_pipeline_compute.c | 4 ++-- src/amd/vulkan/radv_pipeline_graphics.c | 6 +++--- src/amd/vulkan/radv_pipeline_rt.c | 4 ++-- src/amd/vulkan/radv_shader.c | 2 +- src/amd/vulkan/radv_shader.h | 3 ++- src/amd/vulkan/radv_shader_info.c | 23 +++++++++++------------ 7 files changed, 23 insertions(+), 23 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 4eac4fbf839..3e5cde9c794 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -519,10 +519,10 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_key .has_shared2_amd = gfx_level >= GFX7, }; - if (pipeline_key->stage_info[stage->stage].uniform_robustness2) + if (stage->key.uniform_robustness2) vectorize_opts.robust_modes |= nir_var_mem_ubo; - if (pipeline_key->stage_info[stage->stage].storage_robustness2) + if (stage->key.storage_robustness2) vectorize_opts.robust_modes |= nir_var_mem_ssbo; if (!pipeline_key->optimisations_disabled) { diff --git a/src/amd/vulkan/radv_pipeline_compute.c b/src/amd/vulkan/radv_pipeline_compute.c index 1255e935b1f..7122f4055f8 100644 --- a/src/amd/vulkan/radv_pipeline_compute.c +++ b/src/amd/vulkan/radv_pipeline_compute.c @@ -148,8 +148,8 @@ radv_compile_cs(struct radv_device *device, struct vk_pipeline_cache *cache, str /* Run the shader info pass. */ radv_nir_shader_info_init(cs_stage->stage, MESA_SHADER_NONE, &cs_stage->info); - radv_nir_shader_info_pass(device, cs_stage->nir, &cs_stage->layout, pipeline_key, RADV_PIPELINE_COMPUTE, false, - &cs_stage->info); + radv_nir_shader_info_pass(device, cs_stage->nir, &cs_stage->layout, &cs_stage->key, pipeline_key, + RADV_PIPELINE_COMPUTE, false, &cs_stage->info); radv_declare_shader_args(device, pipeline_key, &cs_stage->info, MESA_SHADER_COMPUTE, MESA_SHADER_NONE, &cs_stage->args); diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 3235ebca881..874171ebbd7 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -2102,7 +2102,7 @@ radv_fill_shader_info(struct radv_device *device, const enum radv_pipeline_type consider_force_vrs = radv_consider_force_vrs(pipeline_key, &stages[i], &stages[MESA_SHADER_FRAGMENT]); } - radv_nir_shader_info_pass(device, stages[i].nir, &stages[i].layout, pipeline_key, pipeline_type, + radv_nir_shader_info_pass(device, stages[i].nir, &stages[i].layout, &stages[i].key, pipeline_key, pipeline_type, consider_force_vrs, &stages[i].info); } @@ -2177,8 +2177,8 @@ radv_create_gs_copy_shader(struct radv_device *device, struct vk_pipeline_cache .shader_sha1 = {0}, }; radv_nir_shader_info_init(gs_copy_stage.stage, MESA_SHADER_FRAGMENT, &gs_copy_stage.info); - radv_nir_shader_info_pass(device, nir, &gs_stage->layout, pipeline_key, RADV_PIPELINE_GRAPHICS, false, - &gs_copy_stage.info); + radv_nir_shader_info_pass(device, nir, &gs_stage->layout, &gs_stage->key, pipeline_key, RADV_PIPELINE_GRAPHICS, + false, &gs_copy_stage.info); gs_copy_stage.info.wave_size = 64; /* Wave32 not supported. */ gs_copy_stage.info.workgroup_size = 64; /* HW VS: separate waves, no workgroups */ gs_copy_stage.info.so = gs_info->so; diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c index 86da0d27f94..f28769cedc8 100644 --- a/src/amd/vulkan/radv_pipeline_rt.c +++ b/src/amd/vulkan/radv_pipeline_rt.c @@ -369,8 +369,8 @@ radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache, /* Gather shader info. */ nir_shader_gather_info(stage->nir, nir_shader_get_entrypoint(stage->nir)); radv_nir_shader_info_init(stage->stage, MESA_SHADER_NONE, &stage->info); - radv_nir_shader_info_pass(device, stage->nir, &stage->layout, pipeline_key, RADV_PIPELINE_RAY_TRACING, false, - &stage->info); + radv_nir_shader_info_pass(device, stage->nir, &stage->layout, &stage->key, pipeline_key, RADV_PIPELINE_RAY_TRACING, + false, &stage->info); /* Declare shader arguments. */ radv_declare_shader_args(device, pipeline_key, &stage->info, stage->stage, MESA_SHADER_NONE, &stage->args); diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index a0ce999f8d5..0a17b643317 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -353,7 +353,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st const struct radv_pipeline_key *key, bool is_internal) { unsigned subgroup_size = 64, ballot_bit_size = 64; - const unsigned required_subgroup_size = key->stage_info[stage->stage].subgroup_required_size * 32; + const unsigned required_subgroup_size = stage->key.subgroup_required_size * 32; if (required_subgroup_size) { /* Only compute/mesh/task shaders currently support requiring a * specific subgroup size. diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index bc74781f3d7..bfb49baf3f2 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -989,7 +989,8 @@ struct radv_shader_layout; enum radv_pipeline_type; void radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir, - const struct radv_shader_layout *layout, const struct radv_pipeline_key *pipeline_key, + const struct radv_shader_layout *layout, const struct radv_shader_stage_key *stage_key, + const struct radv_pipeline_key *pipeline_key, const enum radv_pipeline_type pipeline_type, bool consider_force_vrs, struct radv_shader_info *info); diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 27ad95495c6..7939b1af2e5 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -915,7 +915,7 @@ gather_shader_info_rt(const nir_shader *nir, struct radv_shader_info *info) } static void -gather_shader_info_cs(struct radv_device *device, const nir_shader *nir, const struct radv_pipeline_key *pipeline_key, +gather_shader_info_cs(struct radv_device *device, const nir_shader *nir, const struct radv_shader_stage_key *stage_key, struct radv_shader_info *info) { info->cs.uses_ray_launch_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_RAY_LAUNCH_SIZE_ADDR_AMD); @@ -931,10 +931,10 @@ gather_shader_info_cs(struct radv_device *device, const nir_shader *nir, const s * the subgroup size. */ const bool require_full_subgroups = - pipeline_key->stage_info[nir->info.stage].subgroup_require_full || nir->info.cs.has_cooperative_matrix || + stage_key->subgroup_require_full || nir->info.cs.has_cooperative_matrix || (default_wave_size == 32 && nir->info.uses_wide_subgroup_intrinsics && local_size % RADV_SUBGROUP_SIZE == 0); - const unsigned required_subgroup_size = pipeline_key->stage_info[nir->info.stage].subgroup_required_size * 32; + const unsigned required_subgroup_size = stage_key->subgroup_required_size * 32; if (required_subgroup_size) { info->wave_size = required_subgroup_size; @@ -953,10 +953,10 @@ gather_shader_info_cs(struct radv_device *device, const nir_shader *nir, const s } static void -gather_shader_info_task(struct radv_device *device, const nir_shader *nir, const struct radv_pipeline_key *pipeline_key, - struct radv_shader_info *info) +gather_shader_info_task(struct radv_device *device, const nir_shader *nir, + const struct radv_shader_stage_key *stage_key, struct radv_shader_info *info) { - gather_shader_info_cs(device, nir, pipeline_key, info); + gather_shader_info_cs(device, nir, stage_key, info); /* Task shaders always need these for the I/O lowering even if the API shader doesn't actually * use them. @@ -1076,9 +1076,9 @@ radv_nir_shader_info_init(gl_shader_stage stage, gl_shader_stage next_stage, str void radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir, - const struct radv_shader_layout *layout, const struct radv_pipeline_key *pipeline_key, - const enum radv_pipeline_type pipeline_type, bool consider_force_vrs, - struct radv_shader_info *info) + const struct radv_shader_layout *layout, const struct radv_shader_stage_key *stage_key, + const struct radv_pipeline_key *pipeline_key, const enum radv_pipeline_type pipeline_type, + bool consider_force_vrs, struct radv_shader_info *info) { struct nir_function *func = (struct nir_function *)exec_list_get_head_const(&nir->functions); @@ -1193,10 +1193,10 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n switch (nir->info.stage) { case MESA_SHADER_COMPUTE: - gather_shader_info_cs(device, nir, pipeline_key, info); + gather_shader_info_cs(device, nir, stage_key, info); break; case MESA_SHADER_TASK: - gather_shader_info_task(device, nir, pipeline_key, info); + gather_shader_info_task(device, nir, stage_key, info); break; case MESA_SHADER_FRAGMENT: gather_shader_info_fs(device, nir, pipeline_key, info); @@ -1222,7 +1222,6 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n break; } - const struct radv_shader_stage_key *stage_key = &pipeline_key->stage_info[nir->info.stage]; info->wave_size = radv_get_wave_size(device, nir->info.stage, info, stage_key); info->ballot_bit_size = radv_get_ballot_bit_size(device, nir->info.stage, info, stage_key);
